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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Features
The T7630 Dual T1/E1 Terminator consists of two independent, highly integrated, software-configurable, full-featured short-haul transceiver/framers. The T7630 provides glueless interconnection from a T1/E1 line to a digital PCM system. Minimal external clocks are needed. Only a system clock/frame sync and a phase-locked line rate clock are required. System diagnostic and performance monitoring capability with integrated programmable test pattern generator/detector and loopback modes is provided.
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Alarm reporting and performance monitoring per AT&T, ANSI*, and ITU-T standards. Programmable, independent transmit and receive system interfaces at a 2.048 MHz, 4.096 MHz, or 8.192 MHz data rate. System interface master mode for generation of system frame sync from the line source. Internal phase-locked loop (with external VCXO) for generation of system clock from the line source.
Facility Data Link Features
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Power Requirements and Package
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Single 5 V 5% supply. Low power: 375 mW per channel maximum. 144-pin TQFP package. Operating temperature range: -40 C to +85 C.
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HDLC or transparent modes. Automatic transmission and detection of ANSI T1.403 FDL performance report message and bitoriented codes. 64-byte FIFO in both transmit and receive directions.
Microprocessor Interface
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T1/E1 Line Interface Features
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Full T1/E1 pulse template compliance. Receiver provides equalization for up to 11 dB of loss. Digital clock and data recovery. Line coding: B8ZS, HDB3, ZCS, and AMI. Line interface coupling and matching networks for T1 and E1 (120 and 75 ).
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33 MHz, 8-bit data interface, no wait-states. Intel or Motorola interface modes with multiplexed or demultiplexed buses. Directly addressable control registers.
Applications
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T1/E1 Framer Features
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Supports T1 framing modes ESF, D4, SLC (R) -96, T1DM DDS. Supports G.704 basic and CRC-4 multiframe format E1 framing and procedures consistent with G.706. Supports unframed transmission format. T1 signaling modes: transparent; ESF 2-state, 4-state, and 16-state; D4 2-state and 4-state; SLC-96 2-state, 4-state, 9-state and 16-state. E1 signaling modes: transparent and CAS.
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Customer Premises Equipment--CSU/DSU, routers, digital PBX, channel banks (CB), base transceiver stations (BTS-picocell), small switches, and digital subscriber loop access multiplexers (DSLAM). Loop/Access--DLC/IDLC, DCS, BTS (microcell/ macrocell), DSLAMs, and multiplexers (terminal, synchronous/asynchronous, add drop). Central Office--Digital switches, DCS, CB, access concentrators, remote switch modules (RSM), and DSLAMs. Test Equipment--Transmission/BERT tester.
* ANSI is a registered trademark of American National Standards Institute, Inc. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Table of Contents
Contents Page
Features ................................................................................................................................................................... 1 T1/E1 Line Interface Features............................................................................................................................... 1 Power Requirements and Package....................................................................................................................... 1 T1/E1 Framer Features ......................................................................................................................................... 1 Facility Data Link Features.................................................................................................................................... 1 Microprocessor Interface....................................................................................................................................... 1 Applications ........................................................................................................................................................... 1 Feature Descriptions .............................................................................................................................................. 12 T1/E1 Line Interface Features............................................................................................................................. 12 T1/E1 Framer Features ....................................................................................................................................... 12 Facility Data Link Features.................................................................................................................................. 13 User-Programmable Microprocessor Interface ................................................................................................... 13 Functional Description ............................................................................................................................................ 14 Pin Information ....................................................................................................................................................... 18 Line Interface Unit: Block Diagram ......................................................................................................................... 25 Line Interface Unit: Receive ................................................................................................................................... 25 Data Recovery..................................................................................................................................................... 25 Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator .............................................................. 26 Receive Line Interface Configuration Modes ...................................................................................................... 26 Line Interface Unit: Transmit .................................................................................................................................. 32 Output Pulse Generation..................................................................................................................................... 32 LIU Transmitter Configuration Modes ................................................................................................................. 33 LIU Transmitter Alarms ....................................................................................................................................... 33 DSX-1 Transmitter Pulse Template and Specifications ...................................................................................... 34 CEPT Transmitter Pulse Template and Specifications ....................................................................................... 36 Line Interface Unit: Jitter Attenuator ....................................................................................................................... 37 Generated (Intrinsic) Jitter................................................................................................................................... 37 Jitter Transfer Function ....................................................................................................................................... 37 Jitter Accommodation.......................................................................................................................................... 38 Jitter Attenuator Enable (Transmit or Receive Path)........................................................................................... 38 Line Interface Unit: Loopbacks ............................................................................................................................... 41 Full Local Loopback (FLLOOP)........................................................................................................................... 41 Remote Loopback (RLOOP) ............................................................................................................................... 41 Digital Local Loopback (DLLOOP) ...................................................................................................................... 41 Line Interface Unit: Other Features ........................................................................................................................ 41 LIU Powerdown (PWRDN) .................................................................................................................................. 41 Loss of Framer Receive Line Clock (LOFRMRLCK Pin)..................................................................................... 41 In-Circuit Testing and Driver High-Impedance State (3-STATE)......................................................................... 41 LIU Delay Values................................................................................................................................................. 42 SYSCK Reference Clock........................................................................................................................................ 42 Line Interface Unit: Line Interface Networks........................................................................................................... 43 LIU-Framer Interface .............................................................................................................................................. 46 LIU-Framer Physical Interface............................................................................................................................. 46 Interface Mode and Line Encoding...................................................................................................................... 47 DS1: Alternate Mark Inversion (AMI)................................................................................................................... 48 DS1: Zero Code Suppression (ZCS)................................................................................................................... 48 CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 49 Frame Formats ....................................................................................................................................................... 49 T1 Framing Structures......................................................................................................................................... 49
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Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents (continued)
Contents Page
T1 Loss of Frame Alignment (LFA)......................................................................................................................57 T1 Frame Recovery Alignment Algorithms ..........................................................................................................58 T1 Robbed-Bit Signaling ..................................................................................................................................... 59 CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ....................61 CEPT 2.048 Basic Frame Structure.....................................................................................................................62 CEPT Loss of Basic Frame Alignment (LFA).......................................................................................................63 CEPT Loss of Frame Alignment Recovery Algorithm ..........................................................................................63 CEPT Time Slot 0 CRC-4 Multiframe Structure...................................................................................................64 CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) ....................................................................................65 CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms......................................................................66 CEPT Time Slot 16 Multiframe Structure.............................................................................................................70 CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) .........................................................................71 CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm ..............................................................71 CEPT Time Slot 0 FAS/NOT FAS Control Bits ......................................................................................................71 FAS/NOT FAS Si- and E-Bit Source....................................................................................................................71 NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ......................................................................................72 NOT FAS Sa-Bit Sources ....................................................................................................................................72 Sa Facility Data Link Access................................................................................................................................73 NOT FAS Sa Stack Source and Destination........................................................................................................74 CEPT Time Slot 16 X0--X2 Control Bits .............................................................................................................76 Signaling Access.....................................................................................................................................................76 Transparent Signaling..........................................................................................................................................76 DS1: Robbed-Bit Signaling ..................................................................................................................................76 CEPT: Time Slot 16 Signaling.................................................................................................................................77 Auxiliary Framer I/O Timing ....................................................................................................................................78 Alarms and Performance Monitoring.......................................................................................................................81 Interrupt Generation.............................................................................................................................................81 Alarm Definition....................................................................................................................................................81 Event Counters Definition ....................................................................................................................................86 Loopback and Transmission Modes ....................................................................................................................88 Line Test Patterns................................................................................................................................................91 Automatic and On-Demand Commands ..............................................................................................................95 Receive Facility Data Link Interface.....................................................................................................................97 Transmit Facility Data Link Interface..................................................................................................................103 HDLC Operation ................................................................................................................................................104 Transparent Mode..............................................................................................................................................107 Diagnostic Modes ..............................................................................................................................................108 Phase-Lock Loop Circuit .......................................................................................................................................110 Framer-System (CHI) Interface .............................................................................................................................112 DS1 Modes ........................................................................................................................................................112 CEPT Modes......................................................................................................................................................112 Receive Elastic Store.........................................................................................................................................112 Transmit Elastic Store........................................................................................................................................112 Concentration Highway Interface ..........................................................................................................................112 CHI Parameters .................................................................................................................................................113 CHI Frame Timing..............................................................................................................................................115 CHI Offset Programming....................................................................................................................................118 JTAG Boundary-Scan Specification ......................................................................................................................120 Principle of the Boundary Scan..........................................................................................................................120
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Table of Contents (continued)
Contents Page
Test Access Port Controller............................................................................................................................... 121 Instruction Register ........................................................................................................................................... 123 Boundary-Scan Register ................................................................................................................................... 124 BYPASS Register.............................................................................................................................................. 124 IDCODE Register .............................................................................................................................................. 124 3-State Procedures ........................................................................................................................................... 124 Microprocessor Interface ...................................................................................................................................... 125 Overview ........................................................................................................................................................... 125 Microprocessor Configuration Modes................................................................................................................ 125 Microprocessor Interface Pinout Definitions...................................................................................................... 126 Microprocessor Clock (MPCLK) Specifications................................................................................................. 127 Microprocessor Interface Register Address Map .............................................................................................. 127 I/O Timing.......................................................................................................................................................... 127 Reset .................................................................................................................................................................... 134 Hardware Reset (Pin 43/139)............................................................................................................................ 134 Software Reset/Software Restart ...................................................................................................................... 134 Register Architecture ............................................................................................................................................ 135 Global Register Architecture................................................................................................................................. 139 Global Register Structure ..................................................................................................................................... 140 Primary Block Interrupt Status Register (GREG0) ............................................................................................ 140 Primary Block Interrupt Enable Register (GREG1) ........................................................................................... 140 Global Loopback Control Register (GREG2) .................................................................................................... 141 Global Loopback Control Register (GREG3) .................................................................................................... 141 Global Control Register (GREG4) ..................................................................................................................... 142 Device ID and Version Registers (GREG5--GREG7) ...................................................................................... 142 Line Interface Unit (LIU) Register Architecture..................................................................................................... 143 Line Interface Alarm Register ............................................................................................................................... 144 Alarm Status Register (LIU_REG0)................................................................................................................... 144 Line Interface Alarm Interrupt Enable Register .................................................................................................... 144 Alarm Interrupt Enable Register (LIU_REG1) ................................................................................................... 144 Line Interface Control Registers ........................................................................................................................... 145 LIU Control Register (LIU_REG2) ..................................................................................................................... 145 LIU Control Register (LIU_REG3) ..................................................................................................................... 145 LIU Control Register (LIU_REG4) ..................................................................................................................... 146 LIU Configuration Register (LIU_REG5) ........................................................................................................... 147 LIU Configuration Register (LIU_REG6) ........................................................................................................... 147 Framer Register Architecture ............................................................................................................................... 148 Framer Status/Counter Registers...................................................................................................................... 149 FDL Register Architecture .................................................................................................................................... 190 FDL Parameter/Control Registers (800--80E; E00--E0E) .................................................................................. 191 Register Maps ...................................................................................................................................................... 198 Global Registers................................................................................................................................................ 198 Line Interface Unit Parameter/Control and Status Registers ............................................................................ 198 Framer Parameter/Control Registers (Read-Write)........................................................................................... 199 Receive Framer Signaling Registers (Read-Only) ............................................................................................ 201 Framer Unit Parameter Register Map .............................................................................................................. 202 Transmit Signaling Registers (Read/Write) ....................................................................................................... 205 Facility Data Link Parameter/Control and Status Registers (Read-Write)........................................................ 206 Absolute Maximum Ratings................................................................................................................................. 207
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Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents (continued)
Contents Page
Operating Conditions ........................................................................................................................................... 207 Handling Precautions ............................................................................................................................................207 Electrical Characteristics .......................................................................................................................................208 Logic Interface Characteristics...........................................................................................................................208 Power Supply Bypassing ......................................................................................................................................208 Outline Diagram ....................................................................................................................................................209 144-Pin TQFP ....................................................................................................................................................209 Ordering Information .............................................................................................................................................210
Figures
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Figure 1. T7630 Block Diagram (One of Two Channels) .........................................................................................14 Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels) .............................................................16 Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels).............................................................17 Figure 4. Pin Assignment ........................................................................................................................................18 Figure 5. Block Diagram of Line Interface Unit: Single Channel .............................................................................25 Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator...........................................................30 Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator........................................................................30 Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator ........................................................31 Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator .....................................................................31 Figure 10. DSX-1 Isolated Pulse Template .............................................................................................................34 Figure 11. ITU-T G.703 Pulse Template..................................................................................................................36 Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator ..............................................................39 Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator ........................................................................................39 Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator............................................................40 Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator .....................................................................................40 Figure 16. Line Termination Circuitry ......................................................................................................................43 Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits .................................................45 Figure 18. Block Diagram of Framer Line Interface.................................................................................................46 Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing ........................47 Figure 20. T1 Frame Structure ................................................................................................................................50 Figure 21. T1 Transparent Frame Structure ............................................................................................................51 Figure 22. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections........................53 Figure 23. Fs Pattern SLC-96 Superframe Format .................................................................................................53 Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe Structures .............................................................................................................................................................61 Figure 25. CEPT Transparent Frame Structure.......................................................................................................62 Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer ...................................67 Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991) ....................................69 Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode.....73 Figure 29. Transmit and Receive Sa Stack Accessing Protocol..............................................................................75 Figure 30. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode...............................................78 Figure 31. Timing Specification for TFS, TLCK, and TPD in DS1 Mode .................................................................78 Figure 32. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ............................................79 Figure 33. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode ..............................79 Figure 34. Timing Specification for RCRCMFS in CEPT Mode ..............................................................................80 Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ..............................................................80 Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode .................................................80 Figure 37. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode ...........................................81 Lucent Technologies Inc. 5
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Table of Contents (continued)
Figures Page
Figure 38. Relation Between RLCK1 and Interrupt (Pin 99)................................................................................... 81 Figure 39. Timing for Generation of LOPLLCK (Pin 39/143) .................................................................................. 83 Figure 40. The T and V Reference Points for a Typical CEPT E1 Application........................................................ 85 Figure 41. Loopback and Test Transmission Modes............................................................................................... 90 Figure 42. 20-Stage Shift Register Used to Generate the Quasi-Random Signal.................................................. 91 Figure 43. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ................................................. 92 Figure 44. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ....................... 97 Figure 45. Block Diagram for the Receive Facility Data Link Interface ................................................................... 98 Figure 46. Block Diagram for the Transmit Facility Data Link Interface................................................................. 103 Figure 47. Local Loopback Mode ......................................................................................................................... 109 Figure 48. Remote Loopback Mode ..................................................................................................................... 109 Figure 49. T7630 Phase Detector Circuitry .......................................................................................................... 111 Figure 50. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0--bit 2 = 100 (Binary)) ......... 115 Figure 51. CHIDTS Mode Concentration Highway Interface Timing .................................................................... 116 Figure 52. Associated Signaling Mode Concentration Highway Interface Timing ................................................ 117 Figure 53. CHI Timing with ASM and CHIDTS Enabled....................................................................................... 117 Figure 54. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 (CEX = 3 and CER = 4, Respectively) ............................................................................................................... 118 Figure 55. Receive CHI (RCHIDATA) Timing ........................................................................................................ 119 Figure 56. Transmit CHI (TCHIDATA) Timing........................................................................................................ 119 Figure 57. Block Diagram of the T7630's Boundary-Scan Test Logic .................................................................. 120 Figure 58. BS TAP Controller State Diagram........................................................................................................ 121 Figure 59. Mode 1--Read Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................... 130 Figure 60. Mode 1--Write Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................... 130 Figure 61. Mode 2--Read Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................... 131 Figure 62. Mode 2--Write Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................... 131 Figure 63. Mode 3--Read Cycle Timing (MPMODE = 1, MPMUX = 0) ............................................................... 132 Figure 64. Mode 3--Write Cycle Timing (MPMODE = 1, MPMUX = 0) ............................................................... 132 Figure 65. Mode 4--Read Cycle Timing (MPMODE = 1, MPMUX = 1) ............................................................... 133 Figure 66. Mode 4--Write Cycle Timing (MPMODE = 1, MPMUX = 1) ............................................................... 133
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents (continued)
Table Page
Table 1. Pin Descriptions-Channel 1 and Channel 2..............................................................................................19 Table 2. Pin Descriptions-Global ............................................................................................................................23 Table 3. Digital Loss of Signal Standard Select......................................................................................................27 Table 4. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) ..................................27 Table 5. T1/DS1 LIU Receiver Specifications.........................................................................................................28 Table 6. CEPT LIU Receiver Specifications ...........................................................................................................29 Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control ......................................................................32 Table 8. DSX-1 Pulse Template Corner Points (from CB119, T1.102) ...................................................................35 Table 9. DS1 Transmitter Specifications .................................................................................................................35 Table 10. CEPT Transmitter Specifications ............................................................................................................37 Table 11. Loopback Control....................................................................................................................................41 Table 12. SYSCK (16x, CKSEL = 1) Timing Specifications....................................................................................42 Table 13. SYSCK (1x, CKSEL = 0) Timing Specifications......................................................................................42 Table 14. Termination Components by Application.................................................................................................44 Table 15. AMI Encoding .........................................................................................................................................48 Table 16. DS1 ZCS Encoding.................................................................................................................................48 Table 17. DS1 B8ZS Encoding...............................................................................................................................49 Table 18. ITU HDB3 Coding ...................................................................................................................................49 Table 19. T-Carrier Hierarchy..................................................................................................................................49 Table 20. D4 Superframe Format ...........................................................................................................................52 Table 21. DDS Channel-24 Format ........................................................................................................................52 Table 22. SLC-96 Data Link Block Format .............................................................................................................54 Table 23. SLC-96 Line Switch Message Codes .....................................................................................................55 Table 24. Transmit and Receive SLC-96 Stack Structure.......................................................................................55 Table 25. Extended Superframe (ESF) Structure...................................................................................................56 Table 26. T1 Loss of Frame Alignment Criteria ......................................................................................................57 Table 27. T1 Frame Alignment Procedures ............................................................................................................58 Table 28. Robbed-Bit Signaling Options.................................................................................................................59 Table 29. SLC-96 9-State Signaling Format ...........................................................................................................59 Table 30. 16-State Signaling Format ......................................................................................................................60 Table 31. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ......................................................62 Table 32. ITU CRC-4 Multiframe Structure.............................................................................................................64 Table 33. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure ........................................70 Table 34. Transmit and Receive Sa Stack Structure...............................................................................................74 Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ...........................................77 Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................77 Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT .....................................................77 Table 38. Red Alarm or Loss of Frame Alignment Conditions................................................................................82 Table 39. Remote Frame Alarm Conditions............................................................................................................82 Table 40. Alarm Indication Signal Conditions .........................................................................................................82 Table 41. Sa6 Bit Coding Recognized by the Receive Framer-Asynchronous Bit Stream .....................................84 Table 42. Sa6 Bit Coding Recognized by the Receive Framer-Synchronous Bit Stream .......................................85 Table 43. AUXP Synchronization and Clear Sychronization Process ....................................................................85 Table 44. Event Counters Definition .......................................................................................................................86 Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the Primary Loopback Modes ..........................................................................................................89 Table 46. Register FRM_PR69 Test Patterns.........................................................................................................92 Table 47. Register FRM_PR70 Test Patterns.........................................................................................................93 Table 48. Automatic Enable Commands ................................................................................................................95 Table 49. On-Demand Commands .........................................................................................................................96
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Table of Contents (continued)
Table Page
Table 50. Receive ANSI Code ............................................................................................................................... 99 Table 51. Performance Report Message Structure................................................................................................ 99 Table 52. FDL Performance Report Message Field Definition............................................................................. 100 Table 53. Octet Contents and Definition .............................................................................................................. 100 Table 54. Receive Status of Frame Byte.............................................................................................................. 101 Table 55. HDLC Frame Format............................................................................................................................ 104 Table 56. Receiver Operation in Transparent Mode............................................................................................. 108 Table 57. Summary of the T7630's Concentration Highway Interface Parameters .............................................. 113 Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 118 Table 59. TAP Controller States in the Data Register Branch.............................................................................. 122 Table 60. TAP Controller States in the Instruction Register Branch..................................................................... 122 Table 61. T7630's Boundary-Scan Instructions ................................................................................................... 123 Table 62. IDCODE Register................................................................................................................................. 124 Table 63. Microprocessor Configuration Modes .................................................................................................. 125 Table 64. Mode [1--4] Microprocessor Pin Definitions ........................................................................................ 126 Table 65. Microprocessor Input Clock Specifications .......................................................................................... 127 Table 66. T7630 Register Address Map .............................................................................................................. 127 Table 67. Microprocessor Interface I/O Timing Specifications ............................................................................. 128 Table 68. Register Summary ............................................................................................................................... 135 Table 69. Global Register Set (0x000--0x008) ................................................................................................... 139 Table 70. Primary Block Interrupt Status Register (GREG0) (000) ..................................................................... 140 Table 71. Primary Block Interrupt Enable Register (GREG1) (001) .................................................................... 140 Table 72. Global Loopback Control Register (GREG2) (002) .............................................................................. 141 Table 73. Global Loopback Control Register (GREG3) (003) .............................................................................. 141 Table 74. Global Control Register (GREG4) (004) .............................................................................................. 142 Table 75. Device ID and Version Registers (GREG5--GREG7) (005--007) ...................................................... 142 Table 76. Line Interface Units Register Set* ((400--40F); (A00--A0F)).............................................................. 143 Table 77. LIU Alarm Status Register (LIU_REG0) (400, A00) ............................................................................. 144 Table 78. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01) ............................................................. 144 Table 79. LIU Control Register (LIU_REG2) (402, A02) ...................................................................................... 145 Table 80. LIU Control Register (LIU_REG3) (403, A03) ...................................................................................... 145 Table 81. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 3) ...... 146 Table 82. LIU Register (LIU_REG4) (404, A04)................................................................................................... 146 Table 83. LIU Configuration Register (LIU_REG5) (405, A05) ............................................................................ 147 Table 84. Loopback Control ................................................................................................................................. 147 Table 85. LIU Configuration Register (LIU_REG6) (406, A06) ............................................................................ 147 Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 6)........................................... 148 Table 87. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 148 Table 88. Interrupt Status Register (FRM_SR0) (600; C00) ................................................................................ 149 Table 89. Facility Alarm Condition Register (FRM_SR1) (601; C01) ................................................................... 150 Table 90. Remote End Alarm Register (FRM_SR2) (602; C02) .......................................................................... 151 Table 91. Facility Errored Event Register-1 (FRM_SR3) (603; C03) ................................................................... 152 Table 92. Facility Event Register-2 (FRM_SR4) (604; C04) ................................................................................ 153 Table 93. Exchange Termination and Exchange Termination Remote End Interface Status Register (FRM_SR5) (605; C05) ...................................................................................... 154 Table 94. Network Termination and Network Termination Remote End Interface Status Register (FRM_SR6) (606; C06) ...................................................................................... 155 Table 95. Facility Event Register (FRM_SR7) (607; C07) ................................................................................... 156 Table 96. Bipolar Violation Counter Registers (FRM_SR8--FRM_SR9) ((608--609); (C08--C09)) .................. 156 Table 97. Framing Bit Error Counter Registers (FRM_SR10--FRM_SR11) ((60A--60B); (C0A--C0B)) ........... 156
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents (continued)
Table Page
Table 98. CRC Error Counter Registers (FRM_SR12--FRM_SR13) ((60C--60D); (C0C--C0D))......................157 Table 99. E-Bit Counter Registers (FRM_SR14--FRM_SR15) ((60E--60F); (C0E--C0F))................................157 Table 100. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) ((610--611); (C10--C11)) .......................................................................................................................................................157 Table 101. E Bit at NT1 from NT2 Counter (FRM_SR18--FRM_SR19) ((612--613); (C12--C13)) ...................157 Table 102. ET Errored Seconds Counter (FRM_SR20--FRM_SR21) ((614--615); (C14--C15)) ......................158 Table 103. ET Bursty Errored Seconds Counter (FRM_SR22--FRM_SR23) ((616--617); (C16--C17)) ...........158 Table 104. ET Severely Errored Seconds Counter (FRM_SR24--FRM_SR25) ((618--619); (C18--C19))........158 Table 105. ET Unavailable Seconds Counter (FRM_SR26--FRM_SR27) ((61A--61B); (C1A--C1B)) ..............158 Table 106. ET-RE Errored Seconds Counter (FRM_SR28--FRM_SR29) ((61C--61D); (C1C--C1D)) ..............158 Table 107. ET-RE Bursty Errored Seconds Counter (FRM_SR30--FRM_SR31) ((61E--61F); (C1E--C1F)) ....158 Table 108. ET-RE Severely Errored Seconds Counter (FRM_SR32--FRM_SR33) ((620--621); (C20--C21)) ..158 Table 109. ET-RE Unavailable Seconds Counter (FRM_SR34--FRM_SR35) ((622--623); (C22--C23)) ..........159 Table 110. NT1 Errored Seconds Counter (FRM_SR36--FRM_SR37) ((624--625); (C24--C25)) ....................159 Table 111. NT1 Bursty Errored Seconds Counter (FRM_SR38--FRM_SR39) ((626--627); (C26--C27)) .........159 Table 112. NT1 Severely Errored Seconds Counter (FRM_SR40--FRM_SR41) ((628--629); (C28--C29)) .....159 Table 113. NT1 Unavailable Seconds Counter (FRM_SR42--FRM_SR43) ((62A--62B); (C2A--C2B)) ............159 Table 114. NT1-RE Errored Seconds Counter (FRM_SR44--FRM_SR45) ((62C--62D); (C2C--C2D))............159 Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46--FRM_SR47) ((62E--62F); (C2E--C2F))..159 Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48--FRM_SR49 ((630--631); (C30--C31)) .......................................................................................................................................................160 Table 117. NT1-RE Unavailable Seconds Counter (FRM_SR50--FRM_SR51) ((632--633); (C32--C33)) .......160 Table 118. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34) .................................................................160 Table 119. Receive Sa Register (FRM_SR53) (635; C35) ...................................................................................160 Table 120. SLC-96 FDL Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) ........................161 Table 121. CEPT Sa Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) .............................161 Table 122. Transmit Framer ANSI Performance Report Message Status Register Structure ..............................162 Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0--FRM_RSR23) ((640--658); (C40--C58)) .......................................................................................................................................................162 Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0--FRM_RSR31) ((640--65F); (C40--C5F)) .......................................................................................................................................................162 Table 125. Summary of Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) ((660--667); (C60--C67)) .......................................................................................................................................................163 Table 126. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60) .....................................................164 Table 127. Interrupt Enable Register (FRM_PR1) (661; C61)..............................................................................165 Table 128. Interrupt Enable Register (FRM_PR2) (662; C62)..............................................................................165 Table 129. Interrupt Enable Register (FRM_PR3) (663; C63)..............................................................................165 Table 130. Interrupt Enable Register (FRM_PR4) (664; C64)..............................................................................165 Table 131. Interrupt Enable Register (FRM_PR5) (665; C65)..............................................................................165 Table 132. Interrupt Enable Register (FRM_PR6) (666; C66)..............................................................................165 Table 133. Interrupt Enable Register (FRM_PR7) (667; C67)..............................................................................165 Table 134. Framer Mode Bits Decoding (FRM_PR8) (668; C68) .........................................................................166 Table 135. Line Code Option Bits Decoding (FRM_PR8) (668; C68) ..................................................................166 Table 136. CRC Option Bits Decoding (FRM_PR9) (669, C69) ...........................................................................167 Table 137. Alarm Filter Register (FRM_PR10) (66A; C6A) ..................................................................................167 Table 138. Errored Event Threshold Definition.....................................................................................................168 Table 139. Errored Second Threshold Register (FRM_PR11) (66B; C6B) ..........................................................168 Table 140. Severely Errored Second Threshold Registers (FRM_PR12--FRM_PR13) ((66C--66D; C6C--C6D)) .......................................................................................................................................................168 Table 141. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E)...........................................................169
Lucent Technologies Inc.
9
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Table of Contents (continued)
Table Page
Table 142. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F) ..................................... 169 Table 143. NT1 Errored Event Enable Register (FRM_PR16) (670; C70)........................................................... 169 Table 144. NT1 Remote End Errored Event Enable Registers (FRM_PR17--FRM_PR18) ((671--672);(C71--C72))...................................................................................... 169 Table 145. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) .. 170 Table 146. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74) ..................................... 170 Table 147. Framer FDL Control Command Register (FRM_PR21) (675; C75) ................................................... 171 Table 148. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)................................................... 171 Table 149. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77) ...................................... 171 Table 150. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78) ......................................... 172 Table 151. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7--5 ........................................................ 172 Table 152. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79) .................................... 173 Table 153. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6--5 ......................................................... 173 Table 154. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A)............................. 174 Table 155. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 Control Register (FRM_PR27) (67B, C7B)............................................... 175 Table 156. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C).................... 176 Table 157. Sa4--Sa8 Source Register (FRM_PR29) (67D; C7D)....................................................................... 177 Table 158. Sa Bits Source Control for Bit 5--Bit 7 in FRM_PR29 ....................................................................... 177 Table 159. Sa4--Sa8 Control Register (FRM_PR30) (67E; C7E)....................................................................... 178 Table 160. Sa Transmit Stack (FRM_PR31--FRM_PR40) ((67F--688); (C7F--C88)) ....................................... 178 Table 161. SLC-96 Transmit Stack (FRM_PR31--FRM_PR40) ((67F--688); (C7F--C88)) ............................... 179 Table 162. Transmit SLC-96 FDL Format ............................................................................................................ 179 Table 163. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41)(689; C89) ............................................................................................ 179 Table 164. Framer Exercise Register (FRM_PR42) (68A; C8A).......................................................................... 180 Table 165. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (68A; C8A)..................................................................... 180 Table 166. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B) .. 181 Table 167. Signaling Mode Register (FRM_PR44) (68C; C8C)........................................................................... 182 Table 168. CHI Common Control Register (FRM_PR45) (68D; C8D) ................................................................. 183 Table 169. CHI Common Control Register (FRM_PR46) (68E; C8E) ................................................................. 184 Table 170. CHI Transmit Control Register (FRM_PR47) (68F; C8F) ................................................................... 184 Table 171. CHI Receive Control Register (FRM_PR48) (690; C90) .................................................................... 184 Table 172. CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) ((691--694); (C91--C94))... 185 Table 173. CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) ((695--698); (C95--C98)) ... 185 Table 174. CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) ((699--69C); (C99--C9C)) .... 185 Table 175. CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) ((69D--6A0); (C9D--CA0)) .... 186 Table 176. CHI Transmit Control Register (FRM_PR65) (6A1; CA1)................................................................... 186 Table 177. CHI Receive Control Register (FRM_PR66) (6A2; CA2) ................................................................... 186 Table 178. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5) ............................................ 187 Table 179. Pattern Detector Control Register (FRM_PR70) (6A6; CA6) ............................................................. 188 Table 180. Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) ((6E0--6F7); (CE0--CF7)) ................................................................................. 189 Table 181. Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) ((6E0--6FF); (CE0--CFF))................................................................................. 189 Table 182. FDL Register Set (800--80E); (E00--E0E) ....................................................................................... 190 Table 183. FDL Configuration Control Register (FDL_PR0) (800; E00) .............................................................. 191 Table 184. FDL Control Register (FDL_PR1) (801; E01) .................................................................................... 191 Table 185. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) ............................................................ 192 Table 186. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03) ........................................... 193
10
Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents (continued)
Table Page
Table 187. FDL Transmitter FIFO Register (FDL_PR4) (804; E04)......................................................................193 Table 188. FDL Transmitter Idle Character Register (FDL_PR5) (805; E05) .......................................................193 Table 189. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) ..............................................194 Table 190. FDL Register FDL_PR7......................................................................................................................194 Table 191. FDL Receiver Match Character Register (FDL_PR8) (808; E08) .......................................................194 Table 192. FDL Transparent Control Register (FDL_PR9) (809; E09) .................................................................195 Table 193. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A).............................................................195 Table 194. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B).............................................196 Table 195. FDL Transmitter Status Register (FDL_SR1) (80C; E0C)...................................................................197 Table 196. FDL Receiver Status Register (FDL_SR2) (80D; E0D) ......................................................................197 Table 197. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E) ..............................................................197 Table 198. FDL Receiver FIFO Register (FDL_SR4) (807; E07) .........................................................................197 Table 199. Global Register Set.............................................................................................................................198 Table 200. Line Interface Unit Register Set ..........................................................................................................198 Table 201. Framer Unit Status Register Map .......................................................................................................199 Table 202. Receive Signaling Registers Map .......................................................................................................201 Table 203. Framer Unit Parameter Register Map .................................................................................................202 Table 204. Transmit Signaling Registers Map ......................................................................................................205 Table 205. Facility Data Link Register Map ..........................................................................................................206 Table 206. ESD Threshold Voltage.......................................................................................................................207 Table 207. Logic Interface Characteristics (TA = -40 C to +85 C, VDD = 5.0 V 5%, VSS = 0).........................208
Lucent Technologies Inc.
11
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Feature Descriptions
s
s
Two independent T1/E1 channels each consisting of a T1/E1 short-haul line interface and a T1/E1 framer with HDLC formatting on the facility data link interface. Memory-mapped read and write registers. Maskable interrupt events. Hardware and software resets. Onboard software-selectable pseudorandom test pattern generator and detector for line performance monitoring. 3-state outputs. Single 5 V 5% supply. Low power consumption: 750 mW max.
s s s s
Compliant with AT&T CB119(10/79); ITU G.703(88), G.732(88), G.735-9(88), G.823-4(3/93), I.431(3/93); ANSI T1.102(93), T1. 408(90); ETSI, ETS-300-166(8/93), TBR12(12/93, 1/ 96), TBR13(1/96); TR-TSY-000009(5/86), TSY000170(1/93), GR-253-CORE(12/95), GR-499CORE(12/95), GR-820-CORE(11/94), GR-1244CORE(6/95).
T1/E1 Framer Features
s
s s s
T1/E1 Line Interface Features
s
Transmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. Five pulse equalization settings for template compliance at DSX cross connect. Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder. CEPT/E1 interference immunity as required by G.703. Transmit jitter <0.02 UI. Receive generated jitter <0.05 UI. Jitter attenuator selectable for use in transmit or receive path. Jitter attenuation characteristics are data pattern independent. For use with 100 DS1 twisted-pair, 120 E1 twisted-pair, and 75 E1 coaxial cable. Common transformer for transmit/receive. Analog LOS alarm for signals less than -18 dB for greater than 1 ms or 10-bit to 255-bit symbol periods (selectable). Digital LOS alarm for 100 zeros (DS1) or 255 zeros (E1). Diagnostic loopback modes.
s
s
s
s
s s s
s
s s
Framing formats: -- Compliant with T1 standards ANSI T1.231 (1993), AT&T TR54016, AT&T TR62411 (1998). -- Unframed, transparent transmission in T1 and E1 formats. -- DS1 extended superframe (ESF). -- DS1 superframe (SF): D4; SLC-96; T1DM DDS; T1DM DDS with FDL access. -- DS1 independent transmit and receive framing modes when using the ESF and D4 formats. -- Compliant with ITU CEPT framing recommendation: 1. G.704 and G.706 basic frame format. 2. G.704 Section 2.3.3.4 and G.706 Section 4.2: CRC-4 multiframe search algorithm. 3. G.706 Annex B: CRC-4 multiframe search algorithm with 400 ms timer for interworking of CRC-4 and non-CRC-4 equipment. 4. G.706 Section 4.3.2 Note 2: monitoring of 915 CRC-4 checksum errors for loss of frame state. Framer line codes: -- DS1: alternate mark inversion (AMI); binary eight zero code suppression (B8ZS); per-channel zero code suppression; decoding bipolar violation monitor; monitoring of eight or fifteen bit intervals without positive or negative pulses error indication. -- DS1 independent transmit and receive path line code formats when using AMI/ZCS and B8ZS coding. -- ITU-CEPT: AMI; high-density bipolar 3 (HDB3) encoding and decoding bipolar violation monitoring, monitoring of four bit intervals without positive or negative pulses error indication. -- Single-rail option.
s
s
12
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Feature Descriptions (continued)
s
Signaling: -- DS1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. -- DS1: D4 superframe 2-state and 4-state perchannel robbed bit. -- DS1: SLC-96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. -- DS1: channel-24 message-oriented signaling. -- ITU CEPT: channel associated signaling (CAS). -- Transparent (all data channels). Alarm reporting, performance monitoring, and maintenance: -- ANSI T1.403-1995, AT&T TR 54016, and ITU G.826 standard error checking. -- Error and status counters. -- Bipolar violations. -- Errored frame alignment signals. -- Errored CRC checksum block. -- CEPT: received E bit = 0. -- Errored, severely errored, and unavailable seconds. -- Selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. -- CEPT: Selectable automatic transmission of E bit to the line. -- CEPT: Sa6 coded remote end CRC-4 error E bit = 0 events. -- Programmable automatic and on-demand alarm transmission. 1. Automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. Automatic transmission of alarm indication signal (AIS) to the system while in loss of frame alignment state. -- Multiple loopback modes. -- Optional automatic line and payload loopback activate and deactivate modes. -- CEPT nailed-up connect loopback and CEPT nailed-up broadcast transmission TS-X in TS-0 transmit mode. -- Selectable test patterns for line transmission. -- Detection of framed and unframed pseudorandom and quasi-random test patterns. -- Programmable squelch and idle codes. System interface: -- Autonomous transmit and receive system inter-
s
faces. -- Independent transmit and receive frame synchronization input signals. -- Independent transmit and receive system interface clock. -- 2.048 Mbits/s, 2.048 MHz concentration highway interface (CHI) default mode. -- Optional 4.096 Mbits/s and 8.192 Mbits/s data rates. -- Optional 4.096 MHz, 8.192 MHz, and 16.384 MHz frequency system clock. -- Programmable clock edge for latching frame synchronization signals. -- Programmable clock edge for latching transmit and receive data. -- Programmable bit and byte offset. -- Programmable CHI master mode for the generation of the transmit CHI FS from internal logic with timing derived from the receive line clock signal.
s
Digital phase comparator for clock generation in the receive and transmit paths.
Facility Data Link Features
s s
HDLC or transparent mode. Automatic transmission of the ESF performance report messages (PRM). Detection of the ESF PRM. Detection of the ANSI ESF FDL bit-oriented codes. 64-byte FIFO in both transmit and receive directions. Programmable FIFO full- and empty-level interrupt.
s s s s s
SLC-96: FDL transmit and receive register access of D bits.
User-Programmable Microprocessor Interface
s s s s s s
33 MHz read and write access with no wait-states. 12-bit address, 8-bit data interface. Programmable Intel or Motorola interface modes. Demultiplexed or multiplexed address and data bus. Directly addressable internal registers. No clock required.
s
Lucent Technologies Inc. Lucent Technologies Inc.
13
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Functional Description
RECEIVE CHANNEL [1--2] RTIP_RPD[1--2] RECEIVE LINE INTERFACE UNIT (RLIU) RECEIVE FRAMER UNIT RECEIVE ELASTIC STORE (2 FRAMES)
TRANSMIT CONCENTRATION HIGHWAY INTERFACE (TCHI)
TCHICK[1--2] TCHIFS[1--2] TCHIDATA[1--2] TCHIDATAB[1--2]
RRING_RND[1--2]
SYSCK[1--2] RLCK[1--2] TCHICK RLCK RECEIVE CHANNEL DIGITAL PHASE DETECTOR
RFRMCK[1--2], RFRMDATA[1--2], RFS[1--2], RSSFS[1--2], RCRCMFS[1--2] RFDL[1--2], RFDLCK[1--2]
RECEIVE FACILITY DATA LINK MONITOR (HDLC OR TRANSPARENT FRAMING)
RECEIVE SIGNALING UNIT (DS1: ROBBED-BIT OR CEPT: TS16)
DIV-RLCK[1--2], DIV-TCHICK[1--2], TCHICK-EPLL[1--2]
TRANSMIT CHANNEL [1--2] TRANSMIT FACILITY DATA LINK MONITOR (HDLC OR TRANSPARENT FRAMING) PLLCK[1--2] TRANSMIT SIGNALING UNIT (DS1: ROBBED-BIT OR CEPT: TS16) RCHICK TRANSMIT CHANNEL DIGITAL PHASE DETECTOR
DIV-PLLCK[1--2], DIV-RCHICK[1--2], PLLCK-EPLL[1--2]
TFDL[1--2], TFDLCK[1--2] XMIT FRAMER TCLK TTIP[1--2] TRANSMIT LINE INTERFACE UNIT (XLIU) TRANSMIT ELASTIC STORE (2 FRAMES)
TRING[1--2] TND[1--2], TPD[1--2], TLCK[1--2]
TRANSMIT FRAMER UNIT
RECEIVE CONCENTRATION HIGHWAY INTERFACE (RCHI)
RCHICK[1--2] RCHIFS[1--2] RCHIDATA[1--2] RCHDATAB[1--2]
TFS[1--2], TSSFS[1--2], TCRCMFS[1--2]
MICROPROCESSOR INTERFACE
MPMODE MPMUX
A[11:0]
AD[7:0]
CS
ALE_AS
RD_R/W
WR_DS
RDY_DTACK
INTERRUPT
MPCK 5-4512(F).cr.2
Figure 1. T7630 Block Diagram (One of Two Channels)
14
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Functional Description (continued)
The Lucent T7630 Dual T1/E1 Terminator (TerminatorII) provides two complete T1/E1 interfaces each consisting of a fully integrated, full-featured, short-haul line interface transceiver and a full-featured primary rate framer with an HDLC formatter for facility data link access. The T7630 provides glueless interconnection from a T1 or E1 analog line interface to devices interfacing to its CHI; for example, the T7270 Time-Slot Interchanger or T7115A Synchronous Protocol Data Formatter. The line interface receiver performs clock and data recovery using a digital phase-locked loop, thereby avoiding false lock conditions that are common when recovering sparse data patterns with an analog implementation. The receiver's equalization circuit guarantees a high level of interference immunity. The receive line unit monitors the amplitude at the receive input for analog loss of signal (ALOS) detection and the pulse density of the receive signal for digital loss of signal (DLOS) detection. The receive line unit may be programmed to detect bipolar violations. The line interface unit may be optionally bypassed. It is recommended that the LIU/framer interface be placed in dual-rail mode, which allows the framers error/event detector to detect and report code and bipolar violation (BPV) errors. The line interface unit's transmit equalization is done with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. The transmitter will interface to the digital cross connect (DSX) at lengths up to 655 feet for DS1 operation, and line impedances of 75 or 120 for CEPT-E1 operation. The transmit line unit monitors nonfunctional links due to faults at the primary of the transmit transformer and periods of no data transmission. The line codes supported in the framer unit include AMI, T1 B8ZS, per-channel T1 zero code suppression and ITU-CEPT HDB3. The T7630 supports T1 D4, T1DM, and SLC-96 SF, ESF; ITU-CEPT-E1 basic frame; ITU-CEPT-E1 time slot 0 multiframe; and time slot 16 multiframe formats. The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate ANSI, AT&T, and ITU standards. Performance monitoring as specified by AT&T, ANSI, and ITU is provided through counters monitoring bipolar violation, frame bit errors, CRC errors, CEPT E bit = Lucent Technologies Inc. Lucent Technologies Inc.
0 conditions, CEPT Sa6 codes, errored events, errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds. In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected. System, payload, and line loopbacks are programmable. The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock CHI serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be reconfigured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 8.192 MHz clock interface, a 8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface and 16.384 MHz clock interface. The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-oriented signaling (MOS), and ITU-CEPT-E1 channelassociated signaling (CAS). In the T1, RBS mode voice and data channels are programmable. The entire payload can be programmed into a data-only (no signaling channels) mode, i.e., transparent mode. Signaling access can be through the on-chip signaling registers or the system CHI port in the associated signaling mode. Data and its associated signaling information can be accessed through the CHI in either DS1 or CEPT-E1 modes. Extraction and insertion of the facility data link in ESF, T1DM, SLC-96, or CEPT-E1 modes are provided through a four-port serial interface or through a microprocessor-accessed, 64-byte FIFO either with HDLC formatting or transparently. In the T7630's SLC-96 or CEPT-E1 frame formats, a facility data link (FDL) is provided for FDL access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive framer's facility data link unit and are transmitted by the transmit framer FDL The receive framer includes a two-frame elastic store buffer for jitter attenuations that performs control slips and provides indication of slip directions. Accessing internal registers is done via the demultiplexed/multiplexed address and data bus microprocessor interface using either the Intel 80188 (or 80X88) interface protocol with independent read and write signals or the Motorola MC680X0 or M68360 interface protocol with address and data strobe signals. 15
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Functional Description (continued)
The T7630 is manufactured using low-power CMOS technology and is packaged in an 144-pin thin quad flat pack (TQFP) with 20 mils lead pitch.
RLCK FRAMER
RPDE, RNDE, RLCKE RTIP_RPD RECEIVE ANALOG FRONT END RRING_RND DIGITAL CLOCK AND DATA RECOVERY JITTER ATTENUATION (OPTIONAL: RECEIVE OR TRANSMIT)
RPD, RND, RLCK
BPV DECODER AND MONITOR
RPD-LIU, RND-LIU, RLCK-LIU LINE INTERFACE UNIT BYPASS
RECEIVE T1/E1 FRAME ALIGNMENT MONITOR, RE-ALIGNER, AND SYNC GENERATOR: - SF: D4, SLC-96, DDS - ESF - CEPT: BASIC FRAME, CRC-4 MULTIFRAME, & SIGNALING MULTIFRAME RECEIVE PERFORMANCE MONITOR: - BIPOLAR VIOLATION ERRORS - T1/E1 CRC ERRORS - ERRORED EVENTS - ERRORED SECONDS - BURSTY ERRORED SECONDS - SEVERELY ERRORED SECONDS - UNAVAILABLE SECONDS RECEIVE ALARM MONITOR: - ANALOG LOSS OF SIGNAL - DIGITAL LOSS OF SIGNAL - REMOTE FRAME ALARM - CEPT REMOTE MULTIFRAME ALARM - ALARM INDICATION SIGNAL (AIS) - SLIPS RECEIVE PATTERN MONITOR: - QUASI-RANDOM: 220 - 1 - PSEUDORANDOM: 215 - 1 - ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVATE AND DEACTIVATE LINE LOOPBACK CODES - CEPT AUXILIARY PATTERN (CEPT = 01) - CEPT ACTIVATE AND DEACTIVATE LOOPBACK CODES - CEPT Sa6 CODES TEST PATTERN DETECTOR - MARK (ALLONES) - QRSS (QUASI-RANDOM: 220 - 1) - 25 - 1 - 26 - 1 (53) - 29 - 1 (511) - 211 - 1 (2047) - 215 - 1 (PSEUDORANDOM) - 220 - 1 - 223 - 1 - 1:1 (ALTERNATING 10) RECEIVE FACILITY DATA LINK EXTRACTER AND MONITOR: - SLC-96 FORMAT - DDS ACCESS - ANSI T1.403-1989 ESF FORMAT: * BIT-ORIENTED MESSAGES * MESSAGE-ORIENTED MESSAGES RFRMCK RECEIVE SLIP MONITOR INTERNAL SYSTEM CLOCK TCHICK
RECEIVE ELASTIC STORE BUFFER (2 FRAMES)
TRANSMIT CONCENTRATION HIGHWAY INTERFACE (RATE ADAPTER)
TCHIFS TCHIDATA TCHIDATAB
RECEIVE SIGNALING EXTRACTER: - DS1 ROBBED-BIT SIGNALING (RBS) - CEPT CHANNEL ASSOCIATED AND COMMON CHANNEL SIGNALING - CONCENTRATION HIGHWAY ACCESS - MICROPROCESSOR ACCESS RECEIVE FDL HDLC EXTRACTER: - 64-byte RECEIVE FIFO - TRANSPARENT MODE (NO HDLC FRAMING) - MICROPROCESSOR ACCESS
RFDLCK RFDL
5-4513(F).c
Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels)
16
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Functional Description (continued)
SYSCK
/ 16
TLCK, TND, TPD
LOSS OF TLCK TRANSMIT DATA MONITOR
ALL ONES SIGNAL (AIS)
TTIP
PULSE EQUALIZER AND WIDTH CONTROLLER
TRING
JITTER ATTENUATION (OPTIONAL: TRANSMIT OR RECEIVE)
BPV ENCODER (OPTIONAL)
LINE FORMAT ENCODER (AMI; B8ZS; HDB3)
TLCK, TND, TPD
TRANSMIT CRC GENERATOR: - ESF - CEPT TRANSMIT ALARM MONITOR: - LOSS OF SYSTEM BIFRAME ALIGNMENT - SYSTEM ALARM INDICATION SIGNAL (AIS)
TRANSMIT T1/E1 FRAME FORMATTER, AND FRAME SYNC GENERATOR: - SF: D4, SLC-96, DDS; SIGNALING SUPERFRAME - ESF - CEPT: BASIC FRAME, CRC-4 MULTIFRAME, & SIGNALING MULTIFRAME - TRANSPARENT FRAMING
PLLCK TRANSMIT FACILITY DATA LINK INSERTER: TFDL - SLC-96 FORMAT - DDS ACCESS - ANSI T1.403-1989 ESF FORMAT: TFDLCK * BIT-ORIENTED MESSAGES * MESSAGE-ORIENTED MESSAGES TRANSMIT FDL HDLC INSERTER: - 64-byte TRANSMIT FIFO - TRANSPARENT MODE (NO HDLC FRAMING) - MICROPROCESSOR ACCESS
AUTOMATIC AND ON-DEMAND COMMANDS: - AIS (LINE, SYSTEM, FDL) - LOOPBACKS - REMOTE FRAME ALARMS (RFA) - CEPT E BIT = 0 - CEPT TS16 AIS - CEPT TS16 RPA
TRANSMIT SIGNALING INSERTER: - DS1 ROBBED-BIT SIGNALING (RBS) - CEPT CHANNEL ASSOCIATED AND COMMON-CHANNEL SIGNALING - CONCENTRATION HIGHWAY ACCESS - MICROPROCESSOR ACCESS
RCHICK TEST PATTERN GENERATOR - MARK (ALL1s) - QRSS - 25 - 1 - 26 - 1 (53) - 29 - 1 (511) - 211 - 1 (2047) - 215 - 1 - 220 - 1 - 223 - 1 - 1:1 (ALTERNATING 10) TRANSMIT ELASTIC STORE BUFFER (2 FRAMES) RECEIVE CONCENTRATION HIGHWAY INTERFACE (RATE ADAPTER) RCHIFS RCHIDATA RCHIDATAB
5-4514(F).d
Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels)
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17
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Pin Information
The package type and pin assignment for the T7630 (Terminator-II) is illustrated in Figure 4.
TCHIDATA1 TCASDATA1 DIV-RLCK1 DIV-TCHICK1 TCHICK-EPLL1 TFS1 TSSFS1 TCRCMFS1 TFDLCK1 TFDL1 RCHICK1 RCHIFS1 RCHIDATA1
LOPLLCK1 DS1/CEPT1 FRAMER1 3-STATE1 RESET1 TPD1 TND1 TLCK1 RLCK1 RFRMCK1 NC RFRMDATA1 RFS1 RSSFS1 RCRCMFS1 RFDLCK1 RFDL1 TCHICK1 TCHIFS1
RCASDATA1
GRND LORLCK1 SYSCK1 PLLCK-EPLL1 DIV-RCHICK1 DIV-PLLCK1 PLLCK1 GRNDA1 NC RRING_RND1 RTIP_RPD1 NC VDDA1 GRNDX1 TRING1 VDDX1 TTIP1 GRNDX1 GRNDS GRNDX2 TTIP2 VDDX2 TRING2 GRNDX2 VDDA2 NC RTIP_RPD2 RRING_RND2 NC GRNDA2 PLLCK2 DIV-PLLCK2 DIV-RCHICK2 PLLCK-EPLL2 SYSCK2 GRND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD
SECOND GRND
VDD WR_DS TRST TMS TCK TDI TDO MPCK RDY_DTACK INTERRUPT A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE_AS CS MPMUX RD_R/W MPMODE GRND
LORLCK2 LOPLLCK2 DS1/CEPT2 FRAMER2 3-STATE2 RESET2 TPD2 TND2 TLCK2 RLCK2 NC RFRMCK2 RFRMDATA2 RFS2 RSSFS2 RCRCMFS2 RFDLCK2 RFDL2 TCHICK2 TCHIFS2 TCHIDATA2 TCASDATA2 DIV-RLCK2 DIV-TCHICK2
TCHICK-EPLL2 TFS2 TSSFS2 TCRCMFS2 TFDLCK2 TFDL2 RCHICK2
RCHIFS2 RCHIDATA2 RCASDATA2 VDD
VDD
5-4712(F).cr.2
Figure 4. Pin Assignment
18
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Pin Information (continued)
Table 1 and Table 2 show the list of T7630 pins and a functional description for each. Table 1. Pin Descriptions-Channel 1 and Channel 2 Pin
CH1 CH2
Symbol
Type*
Description
1, 36, 73, 109 2 38
GRND LOFRMRLCK
P O
Digital Ground Reference. Loss of Framer Receive Line Clock. This pin is asserted high (1) when the framer internal receive line clock does not toggle for a 250 s interval. Once asserted, this signal is deasserted on the first edge of the framer internal receive line clock. Terminator Mode: (FRAMER, pin 41/141 = 1) LOFRMRLCK is asserted high when SYSCK clock, pin 3/35, is absent. Framer Mode: (FRAMER, pin 41/141 = 0) LOFRMRLCK is asserted high when RLCK clock, pin 47/135, is absent. LIU System Clock. The clock signal used for clock and data recovery and jitter attenuation. This clock must be ungapped and free of jitter. For CKSEL = 1, a 16x clock (for DS1, SYSCK = 24.704 MHz 100 ppm and for CEPT, SYSCK = 32.768 MHz 100 ppm). For CKSEL = 0, a 1x clock (for DS1, SYSCK = 1.544 MHz 100 ppm and for CEPT, SYSCK = 2.048 MHz 100 ppm). Error Phase-Lock Loop Signal. The error signal proportional to the phase difference between DIV-PLLCK and DIV-RCHICK as detected by the internal PLL circuitry (refer to the Phase-Lock Loop Circuit section). Divided-Down RCHI Clock. 32 kHz or 8 kHz clock signal derived from the RCHICK input signal. Divided-Down PLLCK Clock. 32 kHz or 8 kHz clock signal derived from the PLLCK input signal. Transmit Framer Phase-Locked Line Interface Clock. Clock signal used to time the transmit framer. This signal must be phase-locked to RCHICK clock signal and be ungapped and free of jitter. For FRM_PR45, bit 0 (HFLF) = 0, in DS1 PLLCK = 1.544 MHz and in CEPT PLLCK = 2.048 MHz. For FRM_PR45, bit 0 (HFLF) = 1 in DS1 PLLCK = 6.176 MHz and in CEPT PLLCK = 8.192 MHz. Analog Ground Reference. No Connection. Receive Bipolar Ring. Negative bipolar input data from the receive analog line isolation transformer. Receive Negative Rail Data. Valid when the FRAMER pin is strapped to 0 V. Nonreturn-to-zero (NRZ) serial data latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. In the single-rail mode, when RND = 1 the receive bipolar violation counter increments once for each rising edge of RLCK.
3
35
SYSCK
Iu
4
34
PLLCK-EPLL
O
5 6 7
33 32 31
DIV-RCHICK DIV-PLLCK PLLCK
O O I
8
30
GRNDA NC RRING_RND
P -- I
9, 12, 19, 26, 29 10 28
* Iu indicates an internal pull-up. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 1. Pin Descriptions-Channel 1 and Channel 2 (continued) Pin
CH1 CH2
Symbol
Type*
Description
11
27
RTIP_RPD
I
Receive Bipolar Tip. Positive bipolar input data from the receive analog line isolation transformer. Receive Positive Rail Data. Valid when the FRAMER pin is strapped to 0 V. NRZ serial data latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional single-rail NRZ receive data latched by the rising edge of RLCK. Analog 5 V Power Supply. 5 V 5%. Transmit Line Driver Ground Reference. Transmit Bipolar Ring. Negative bipolar output data to the transmit analog isolation transformer. Transmit Line Driver 5 V Power Supply. 5 V 5%. Transmit Bipolar Tip. Positive bipolar output data to the transmit analog isolation transformer. 5 V Power Supply. 5 V 5%. Loss of PLLCK Clock. This pin is asserted high when the PLLCK clock does not toggle for a 250 s interval. This pin is deasserted 250 s after PLLCK clock restarts toggling. DS1/CEPT. Strap to VDD to enable defaults for DS1 operation. Strap to VSS to enable defaults for CEPT operation. Framer Mode. Strap to VDD to enable integrated LIU and framer operation. Strap to VSS to bypass the LIU section; the receive framer is sourced directly from the RPD, RND, and RLCK pins while the TPD, TND, and TLCK pins are driven by the transmit framer. 3-State (Active-Low). Asserting this pin low forces the channel outputs into a high-impedance state. Asserting both 3-state pins low forces all outputs into a high-impedance state. Reset (Active-Low). Asserting this pin low resets the channel. Asserting both RESET pins low resets the entire device including the global registers. Transmit Line Interface Positive-Rail Data. This signal is the transmit framer positive NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TPD = transmit framer data.
13 14, 18 15 16 17
25 20, 24 23 22 21
VDDA GRNDX TRING VDDX TTIP VDD LOPLLCK
P P O P O P O
37, 72, 108, 144 143 39
142 141
40 41
DS1/CEPT FRAMER
Iu Iu
140
42
3-STATE
Iu
139
43
RESET
Iu
138
44
TPD
O
*
Iu indicates an internal pull-up. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
20
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Pin Information (continued)
Table 1. Pin Descriptions-Channel 1 and Channel 2 (continued) Pin
CH1 CH2
Symbol
Type*
Description
137
45
TND
O
Transmit Line Interface Negative-Rail Data. This signal is the transmit framer negative NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TND = 0. Transmit Framer Line Interface Clock. Optional 1.544 MHz DS1 or 2.048 MHz output signal from the transmit framer. TND and TPD data changes on the rising edge of TLCK. Receive Framer Line Interface Clock. Valid when the FRAMER pin is strapped to 0 V. This is the 1.544 MHz DS1 or 2.048 MHz input clock signal used by the receive framer to latch RPD and RND data. Receive Framer Clock. Output receive framer clock signal used to clock out the receive framer output signals. In normal operation, this is the recovered receive line clock signal. LIU System Clock Mode. This pin selects either a 16x rate clock for SYSCK (CKSEL = 1) or a primary line rate clock for SYSCK (CKSEL = 0). Receive Framer Data. This signal is the decoded data input to the receive elastic store. During loss of frame alignment, this signal is forced to 1. Receive Frame Sync. This active-high signal is the 8 kHz frame synchronization pulse generated by the receive framer. Receive Framer Signaling Superframe Sync. This active-high signal is the CEPT signaling superframe (multiframe) synchronization pulse in the receive framer. Receive Framer CRC-4 Multiframe Sync. This active-high signal is the CEPT CRC-4 multiframe synchronization pulse in the receive framer. Receive Facility Data Link Clock. In DS1-DDS with data link access, this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal. The receive data link bit changes on the falling edge of RFDLCK. Receive Facility Data Link. Serial output facility data link bit stream extracted from the receive line data stream by the receive framer. In DS1DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In the CEPT frame format, RFDL can be programmed to one of the Sa bits of the NOT FAS frame TS0. During loss of frame alignment, this signal is 1. TransmitrCHI Clock. 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. This clock must be free of jitter. Transmit CHI Frame Sync. Transmit CHI 8 kHz input frame synchronization pulse phase-locked to TCHICK. In the CHI master mode, the transmit CHI generates the 8 kHz frame sync to control the CHI.
136
46
TLCK
O
135
47
RLCK
I
134
49
RFRMCK
O
133 132 131 130
48 50 51 52
CKSEL RFRMDATA RFS RSSFS
Iu O O O
129 128
53 54
RCRCMFS RFDLCK
O O
127
55
RFDL
O
126
56
TCHICK
I
125
57
TCHIFS
I/O
*
Iu indicates an internal pull-up. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 1. Pin Descriptions-Channel 1 and Channel 2 (continued) Pin
CH1 CH2
Symbol
Type*
Description
124
58
TCHIDATA
O
Transmit CHI Data. Serial output system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance state for all inactive time slots. Transmit CHI Data B. Serial output system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance state for all inactive time slots. Divided-Down Receive Line Clock. 8 kHz clock signal derived from the recovered receive line interface unit clock or the RLCK input signal. Divided-Down CHI Clock. 8 kHz clock signal derived from the transmit CHI CLOCK input signal. Error Phase-Lock Loop Signal. The error signal proportional to the phase difference between DIV-TCHICK and DIV-RLCK as detected from the internal PLL circuitry (refer to the Phase-Lock Loop Circuit section. Transmit Framer Frame Sync. This signal is the 8 kHz frame synchronization pulse in the transmit framer. This signal is active-high. Transmit Framer Signaling Superframe Sync. This signal is the CEPT signaling superframe (multiframe) synchronization pulse in the transmit framer. This signal is active-high. Transmit Framer CRC-4 Multiframe Sync. This signal is the CEPT CRC-4 submultiframe synchronization pulse in the transmit framer. This signal is active-high. Transmit Facility Data Link Clock. In DS1-DDS with data link access, this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame latches data link bits on the falling edge of TFDLCK. Transmit Facility Data Link. Optional serial input facility data link bit stream inserted into the transmit line data stream by the transmit framer. In DS1DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be programmed to one of the Sa bits of the NOT-FAS frame time slot 0. Receive CHI Clock. 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. This clock must be free of jitter. Receive CHI Frame Sync. Receive CHI 8 kHz frame synchronization pulse phase-locked to RCHICK. Receive CHI Data. Serial input system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. Receive CHI Data B. Serial input system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
123
59
TCHIDATAB
O
122 121 120
60 61 62
DIV-RLCK DIV-TCHICK TCHICK-EPLL
O O O
119 118
63 64
TFS TSSFS
O O
117
65
TCRCMFS
O
116
66
TFDLCK
O
115
67
TFDL
I
114 113 112 111
*
68 69 70 71
RCHICK RCHIFS RCHIDATA RCHIDATAB
I I I I
Iu indicates an internal pull-up. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Pin Information (continued)
Table 2. Pin Descriptions-Global Pin 74 Symbol MPMODE Type* Iu Description MPMODE. Strap to ground to enable the Motorola 68360 microprocessor protocol (MODE1 or MODE2). Strapped to VDD to enable the Intel 80X86/88 microprocessor protocol (MODE3 or MODE4). Read (Active-Low). In the Intel interface mode, the T7630 drives the data bus with the contents of the addressed register while RD is low. Read/Write. In the Motorola interface mode, this signal is asserted high for read accesses; this pin is asserted low for write accesses. MPMUX. Strap to VSS to enable the demultiplexed address and data bus mode. Strap to VDD to enable the multiplexed address and data bus mode. Chip Select (Active-Low). In the Intel interface mode, this pin must be asserted low to initiate a read or write access and kept low for the duration of the access; asserting CS low forces RDY out of its high-impedance state into a 0 state. Address Latch Enable/Address Strobe. In the address/data bus multiplex mode of the microprocessor, when this signal transitions from high to low, the state of the address bus is latched into internal address registers. In the demultiplexed address mode, the address is transparent through the T7630 and is latched on the rising edge of the ALE_AS signal. Alternatively, if ALE_AS is not connected to the micropressor or other driver, it must be connected to ground. Microprocessor Address_Data Bus. Multiplexed address and bidirectional data bus used for read and write accesses. High-impedance output. Microprocessor Address Bus. Address bus used to access the internal registers. Interrupt. INTERRUPT is asserted high indicating an internal interrupt condition/event has been generated. Otherwise, INTERRUPT is 0. Interrupt events/conditions are maskable through the control registers. Interrupt assertion may be inverted (active-low) by setting register GREG 4 bit 6 = 1. This output may not be wire OR connected to any other logic output.
75
RD_R/W
I
76 77
MPMUX CS
Iu I
78
ALE_AS
I
79--86 87--98 99
AD0--AD7 A0--A11 INTERRUPT
I/O I O
*
Iu indicates an internal pull-up. Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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23
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions-Global (continued) Pin 100 Symbol RDY_DTACK Type* O Description Ready. In the Intel interface mode, this pin is asserted high to indicate the completion of a read or write access; this pin is forced into a high-impedance state while CS is high. Data Transfer Acknowledge (Active-Low). In the Motorola interface mode, DTACK is asserted low to indicate the completion of a read or write access; DTACK is 1 otherwise. Microprocessor Clock. Microprocessor clock used in the Intel mode to generate the READY signal. JTAG Data Output. Serial output data sampled on the falling edge of TCK from the boundary-scan test circuitry. JTAG Data Input. Serial input data sampled on the rising edge of TCK for the boundary-scan test circuitry. JTAG Clock Input. TCK provides the clock for the boundary-scan test logic. JTAG Mode Select (Active-High). The signal values received at TMS are sampled on the rising edge of TCK and decoded by the boundary-scan TAP controller to control boundary-scan test operations. JTAG Reset Input (Active-Low). Assert this pin low to asynchronously initialize/reset the boundary-scan test logic. Write (Active-Low). In the Intel mode, the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to WR. Data Strobe (Active-Low). In the Motorola mode, when AS is low and R/W is low (write), the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to DS; when AS is low and R/W is high (read), the T7630 drives the data bus with the contents of the addressed register while DS is low. Second Pulse. A one second timer with an active-high pulse. The duration of the pulse is one RLCK cycle. The received line clock of FRAMER1 (RLCK1) is the default clock source for the internal second pulse timer. When LOFRMCLK1 is active, the received line clock of FRAMER2 is used as the clock signal source for the internal second pulse timer. The second pulse is used for performance monitoring.
101 102 103 104 105
MPCK JTAGTDO JTAGTDI JTAGTCK JTAGTMS
Iu O Iu Iu Iu
106 107
JTAGTRST WR_DS
Id I
110
SECOND
O
* Iu indicates an internal pull-up. Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
24
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Line Interface Unit: Block Diagram
The T7630 LIU diagram is shown in Figure 5. Only a single transceiver is shown here for illustration purposes.
RALOS (UNCOMMITTED FEATURE) LINE LENGTH INDICATOR RND_BPV RTIP RRING EQUALIZER SLICERS CLOCK AND DATA RECOVERY JITTER ATTENUATOR (RECEIVE PATH) DECODER RPD TO RECEIVE FRAMER RLCK FLLOOP (DURING LIU AIS) FLLOOP (NO LIU AIS) TDM (CLOCK) LOTC PULSEWIDTH CONTROLLER TLCK-LIU RDLOS
DLLOOP
RLOOP
TTIP TRANSMIT DRIVER TRING ALARM INDICATION SIGNAL (AIS) PULSE EQUALIZER (DATA)
JITTER ATTENUATOR (TRANSMIT PATH) ENCODER
TND-LIU TPD-LIU FROM TRANSMIT FRAMER
LBO 0.0 db 7.5 db 15.0 db 22.5 db
LOSS OF TLCK
DIVIDE BY 16 SYSCK LOSS OF SYSCK MONITOR 5-4556(F).g
Figure 5. Block Diagram of Line Interface Unit: Single Channel
Line Interface Unit: Receive
Data Recovery
The receive line-interface unit (RLIU) transmission format is bipolar alternate mark inversion (AMI). The RLIU accepts input data with a data rate tolerance of 130 ppm (DS1) or 80 ppm (E1). The RLIU first restores the incoming data and detects ALOS. Subsequent processing is optional and depends on the programmable LIU configuration established within the microprocessor interface registers. The RLIU utilizes an adaptive equalizer to operate on line length with typically up to 3615 dB of loss at 772 kHz (T1/DS1) or 4313 dB loss at 1.024 MHz (E1). The signal is then peak-detected and sliced to produce digital representations of the data. Selectable DLOS, jitter attenuation, and data decoding are performed.
The clock is recovered by a digital phase-locked loop that uses SYSCK as a reference to lock to the data rate component. Because the reference clock is a multiple of the received data rate, the internal RLCK (RLCKLIU) output will always be a valid DS1/CEPT clock that eliminates false lock conditions. During periods with no receive input signal from the line, the free-run frequency of RLCK-LIU is defined to be either SYSCK/16 or SYSCK depending on the state of CKSEL. RLCKLIU is always active with a duty cycle centered at 50%, deviating by no more than 5%. Valid data is recovered within the first few bit periods after the application of SYSCK.
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25
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Receive (continued)
Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator
The RLIU is designed to accommodate large amounts of input jitter. The RLIU's jitter performance exceeds the requirements shown in the RLIU specification Table 5 and Table 6. Typical receiver performance without the jitter attenuator in the path is shown in Figures 6--9. Typical receiver performance with the jitter attenuator is given in Figures 12--15. Jitter transfer is independent of input ones density on the line interface.
will latch the alarm and remain set until being cleared by a read (clear on read). Upon the transition from ALOS = 0 to ALOS = 1, a microprocessor interrupt will be generated if the ALOS interrupt enable bit ALOSIE (register LIU_REG1, bit 0) is set. The reset default is ALOSIE = 0. The ALOS circuitry provides 4 dB of hysteresis to prevent alarm chattering. The time required to detect ALOS is selectable. When ALTIMER = 0 (register LIU_REG4, bit 0), ALOS is declared between 1 ms and 2.6 ms after losing signal as required by I.431(3/93) and ETS-300-233 (5/94). If ALTIMER = 1, ALOS is declared between 10-bit and 255-bit symbol periods after losing signal as required by G.775 (11/95). The timing is derived from the SYSCK clock. The detection time is independent of signal amplitude before the loss condition occurs. Normally, ALTIMER = 1 would be used only in E1 mode since no T1/DS1 standards require this mode. In T1/DS1 mode, this bit should normally be zero. The reset default is ALTIMER = 0. The behavior of the receiver RLIU outputs under ALOS conditions is dependent on the loss shutdown (LOSSD) control bit (register LIU_REG3, bit 4) in conjunction with the receive alarm indication select (RCVAIS) control bit (register LIU_REG4, bit 1) as described in the Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS) section on page 27. When operating on long-haul loops, the receive input signal will routinely be well below the 20 dB ALOS level. Therefore, when the transmit equalization is programmed to any of the longhaul settings shown in Table 8, the ALOS function is completely disabled. Digital Loss of Signal (DLOS) Alarm. A (DLOS) detector guarantees the received signal quality as defined in the appropriate ANSI, Bellcore, and ITU standards. The DLOS alarm is reported in the RLIU alarm status register (register LIU_REG0, bit 1). For DS1 operation, digital loss of signal (DLOS = 1) is indicated if 100 or more consecutive zeros occur in the receive data stream. The DLOS condition is deactivated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. The DLOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). The LOSSTD control bit (register LIU_REG2, bit 2) selects the conformance protocols for the DLOS alarm indication per Table 3. Setting LOSSTD = 1 adds an additional constraint that there are less than 15 consecutive zeros in the DS1 data stream before DLOS is deactivated. The reset default is LOSSTD = 0.
Receive Line Interface Configuration Modes
Zero Substitution Decoding (CODE) When single-rail operation is selected with DUAL = 0 (register LIU_REG3, bit 3), the LIU B8ZS/HDB3 zero substitution decoding can be selected via the CODE bit (register LIU_REG3, bit 2). If CODE = 1, the B8ZS/ HDB3 decoding function is enabled in the receive path. Decoded receive data appears at the internal LIU-toframer RPD interface (RPD-LIU). Code violations, including BPVs, appear at the internal LIU-to-framer RND_BPV interface (RND-LIU). If CODE = 0, the receive data is passed unaltered to RPD-LIU, and all bipolar violations (such as two consecutive ones if the same polarity) appear at RND-LIU. The default configuration is single-rail, DUAL = 0, with the decoding active, CODE = 1. If DUAL = 0, the receive framer must be programmed to the single-rail mode and the receive framer's internal LIU-to-framer RPD input will be the receive data port. If DUAL = 0, then the receive framer's bipolar violation count will increment by one whenever the internal LIUto-framer RND_BPV signal is one. The bipolar violation count is incremented on the rising edge of the receive framer's RLCK clock signal. Receive Line Interface Unit (RLIU) Alarms Analog Loss of Signal (ALOS) Alarm. An analog signal detector monitors the receive signal amplitude and reports its status in the ALOS alarm bit ALOS (register LIU_REG0, bit 0). ALOS is indicated (ALOS = 1) if the amplitude at the RRING and RTIP inputs drops below a voltage approximately 18 dB below the nominal signal amplitude. The ALOS alarm condition will clear when the receive signal amplitude returns to a level greater than 14 dB below normal. The ALOS alarm status bit 26
Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
mined state when a DLOS or ALOS alarm occurs. If LOSSD = 0 and RCVAIS = 0, the RND-LIU, RPDLIU, and RLCK-LIU signals will be unaffected by the DLOS alarm condition. However, when an ALOS alarm condition is indicated in the LIU alarm status register (register LIU_REG0, bit 0), the RPD-LIU and RND-LIU signals are forced to 0 state and the RLCK-LIU free runs (at the INTSYSCK/16 frequency). If LOSSD = 1, RCVAIS = 0, and a DLOS alarm condition is indicated in the LIU alarm status register (register LIU_REG0, bit 1) or an ALOS alarm condition is indicated, the RPD-LIU and RND-LIU signals are forced to the inactive (dependent on ALM) and the RLCK-LIU free runs (at the INTSYSCK/16 frequency). If LOSSD = 0, RCVAIS = 1, and a DLOS or an ALOS alarm condition is indicated in the LIU alarm status register (register LIU_REG0, bits 0 or 1), the RPD-LIU and RND-LIU signals will present an alarm indication signal (AIS, all ones) based on the free-running INTSYSCK/ 16 frequency. If LOSSD = 1, RCVAIS = 1, and a DLOS or an ALOS alarm condition is indicated in LIU alarm status register (register LIU_REG0, bits 0 or 1), the RPD-LIU and RND-LIU signals are forced to inactive (dependent on ALM) and the RLCK-LIU free runs at the INTSYSCK/ 16 frequency. The RND-LIU, RPD-LIU, and RLCK-LIU signals will be remain unaffected if any loopback (FLLOOP, RLOOP , DLLOOP) is activated independent of LOSSD and RCVAIS settings. The default reset state is LOSSD = 0 and RCVAIS = 0. The LOSSD and RCVAIS behavior is summarized in Table 4.
Line Interface Unit: Receive (continued)
For E1 operation, DLOS is indicated when 255 or more consecutive zeros occur in the receive data stream. The DLOS indication is deactivated when the average ones density of at least 12.5% is received in 255 contiguous pulse positions. LOSSTD has no effect in E1 mode. Upon the transition from DLOS = 0 to DLOS = 1, a microprocessor interrupt will be generated if the DLOS interrupt enable bit DLOSIE (register LIU_REG1, bit 1) is set. The reset default is DLOSIE = 0. The DLOS alarm may occur when FLLOOP is activated (see Line Interface Unit: Loopbacks) due to the abrupt change in signal level at the receiver input. Setting the FLLOOP alarm prevention PFLALM = 1 (register LIU_REG 4, bit 2) prevents the DLOS alarm from occurring when FLLOOP is activated by quickly resetting the receiver's internal peak detector. It will not prevent the DLOS alarm during the FLLOOP period but only avoids the alarm created by the signal amplitude transient. The reset default is PFLALM = 0. Table 3. DLOS Standard Select LOSSTD 0 1 DS1 Mode T1M1.3/93-005, ITU-T G.775 TR-TSY-000009 CEPT Mode ITU-T G.775 ITU-T G.775
Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS). The loss shutdown (LOSSD) control bit (register LIU_REG3, bit 4) acts in conjunction with the receive alarm indication select (RCVAIS) control bit (register LIU_REG4, bit 1) to place the digital RLIU signals (RPD-LIU, RND-LIU, RLCK-LIU) in a predeter-
Table 4. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) LOSSD 0 0 1 1 0 0 1 1 RCVAIS 0 0 0 0 1 1 1 1 ALARM ALOS DLOS ALOS DLOS ALOS DLOS ALOS DLOS RPD/RND Inactive (1/0 dependent on ALM) Normal Data Inactive (1/0 dependent on ALM) Inactive (1/0 dependent on ALM) AIS (all ones) AIS (all ones) Inactive (1/0 dependent on ALM) Inactive (1/0 dependent on ALM) RLCK Free Runs Recovered Clock Free Runs Free Runs Free Runs Free Runs Free Runs Free Runs
LIU Receiver BPV Alarm. The receiver LIU BPV alarm is used only in the single-rail mode. When B8ZS(DS1)/ HDB3(E1) coding is not used (i.e., CODE = 0), any violations in the receive data (such as two or more consecutive ones on a rail) are indicated on the RND-LIU output. When B8ZS(DS1)/HDB3(E1) coding is used (i.e., CODE = 1), the HDB3/B8ZS code violations, as defined in the appropriate standards, are reflected on the RND-LIU output. Lucent Technologies Inc. Lucent Technologies Inc. 27
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Receive (continued)
During T1/DS1 operation, the LIU receiver will perform as specified in Table 5. Table 5. T1/DS1 LIU Receiver Specifications Parameter Analog Loss of Signal: Threshold to Assert Threshold to Clear Hysteresis Time to Assert (ALTIMER = 0) Receiver Sensitivity2 Jitter Transfer: 3 dB Bandwidth Peaking Generated Jitter Jitter Accommodation Return Loss:3 51 kHz to 102 kHz 102 kHz to 1.544 MHz 1.544 MHz to 2.316 MHz Digital Loss of Signal: Flag Asserted When Consecutive Bit Positions Contain Flag Deasserted when Data Density Is and Maximum Consecutive Zeros Are 12.5 -- -- -- -- -- -- 15 99 %ones zeros zeros -- TR-TRY-000009 ITU-T G.775, T1M1.3/ 93-005 100 -- -- zeros ITU-T G.775, T1M1.3/93-005 Min 23 17.5 -- 1.0 11 -- -- -- -- Typ 18 14 4 15 3.84 -- 0.04 -- Max 16.5 12.5 -- 2.6 -- -- 0.1 0.05 -- Unit dB1 dB1 dB ms dB kHz dB UIp-p -- Spec I.431 -- -- I.431 -- Figure 7 Figure 13 TR-TSY-000499, ITU-T G.824 Figure 6 Figure 12 -- -- --
14 20 16
-- -- --
-- -- --
dB dB dB
1. Below the nominal pulse amplitude of 3.0 V with the line interface circuitry specified in the Line Interface Unit: Line Interface Networks section. 2. Cable loss at 772 kHz. 3. Using Lucent transformer 2795B and components listed in Table 14.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Receive (continued)
During E1 operation, the LIU receiver will perform as specified in Table 6. Table 6. CEPT LIU Receiver Specifications Parameter Analog Loss of Signal: Threshold to Assert Threshold to Clear Hysteresis Time to Assert (ALTIMER = 0) Time to Assert (ALTIMER = 1) Receiver Sensitivity2 Interference Immunity:
3
Min 23 17.5 -- 1.0 10 11 9 -- -- -- --
Typ 18 14 4 -- -- 13.5 12 5.1 -- 0.04 --
Max 16.5 12.5 -- 2.6 255 -- -- -- 0.5 0.05 --
Unit dB1 dB1 dB ms UI dB dB kHz dB UIp-p --
Specification I.431, ETSI 300 233 -- -- I.431, ETSI 300 233 G.775 -- ITU-T G.703 Figure 9 Figure 15 ITU-T G.823, I.431 Figure 8 Figure 14 ITU-T G.703
Jitter Transfer: 3 dB Bandwidth, Single-pole Roll Off Peaking Generated Jitter Jitter Accommodation Return Loss:4 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Digital Loss of Signal: Flag Asserted When Consecutive Bit Positions Contain Flag Deasserted When Data Density Is (LOSSTD = 1)
14 20 16 255 12.5
-- -- -- -- --
-- -- -- -- --
dB dB dB zeros %ones
-- ITU-T G.775
1. Below the nominal pulse amplitude of 3.0 V for 120 and 2.37 V for 75 applications with the line circuitry specified in the Line Interface Unit: Line Interface Networks section. 2. Cable loss at 1.024 MHz. 3. Amount of cable loss for which the receiver will operate error-free in the presence of a -18 dB interference signal summing with the intended signal source. 4. Using Lucent transformer 2795D or 2795C and components listed in Table 14.
Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Receive (continued)
100 UI
28 UI
T1.408/I.431(DS1)/G.824(DS1)
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
10 UI
GR-499-CORE (NON-SONET CAT II INTERFACES)
I.431(DS1), G.824(DS1)
1.0 UI
TR-TSY-000009 (DS1, MUXes) GR-499/1244-CORE (CAT I INTERFACES)
0.1 UI
1
10
100
1k
10k
100k
FREQUENCY (Hz)
5-5260(F)
Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator
GR-499-CORE (NON-SONET CAT II TO CAT II) 0 TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
10
JITTER OUT/JITTER IN (dB)
20
30
40
50
60
1
10
100
1k
10 k
100 k
FREQUENCY (Hz)
5-5261(F)
Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator 30 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Receive (continued)
100 UI G.823 37 UI
I.431(CEPT)/ETS-300-011
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION) 10 UI
G.823,ETS-300-011A1 1.0 UI
I.431(CEPT)/ETS-300-011
0.1 UI
1
10
100
1k
10k
100k
FREQUENCY (Hz)
5-5262(F)r.9
Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator
G.735-9 WITHOUT JITTER REDUCER 0
10
JITTER OUT/JITTER IN (dB)
20
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
30
40
50
60
1
10
100
1k
10k
100k
5-5263(F)
FREQUENCY (HZ)
Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Line Interface Unit: Transmit
Output Pulse Generation
The line interface transmitter accepts a line rate clock and NRZ data in single-rail mode (DUAL = 0) or positive and negative NRZ data in dual-rail mode (DUAL = 1) from the transmit framer unit or, optionally, the system interface. The line interface transmitter converts this data to a balanced bipolar signal (AMI format) with optional B8ZS(DS1)/HDB3(E1) encoding and optional jitter attenuation. Low-impedance output drivers produce the line transmit pulses. Positive ones are output as positive pulses on TTIP and negative ones are out, put as positive pulses on TRING. Binary zeros are converted to null pulses. In DSX-1 applications, transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse
equalizer. The pulse-width controller produces highspeed timing signals to accurately control the transmit pulse widths. This eliminates the need for a tightly controlled transmit clock duty cycle that is usually required in discrete implementations. The pulse equalizer controls the amplitudes and shapes of the pulses. Different pulse equalizations are selected through settings of EQ2, EQ1, and EQ0 bits (register LIU_REG6, bits 0 to 2) as described in Table 7, Transmit Line Interface Short-Haul Equalizer/Rate Control below. The reset default state of the equalization bits EQ2, EQ1, and EQ0 can be predetermined by setting the DS1_CEPT pin. The default transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1; EQ2, EQ1, and EQ0 = 110 (CEPT 120 /75 ) when DS1_CEPT = 0. This feature aids in transmitting AIS at the correct rate upon completion of hardware reset; See LIU transmitter alarm indication signal generator (XLAIS) on Table 33.
Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control Short-Haul Applications EQ2 EQ1 EQ0 Service Clock Rate Transmitter Equalization* Maximum Cable Loss to DSX dB 0.6 1.2 1.8 2.4 3.0 --
Feet 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CEPT 2.048 MHz DSX-1 1.544 MHz 0 to 131 131 to 262 262 to 393 393 to 524 524 to 655
Meters 0 to 40 40 to 80 80 to 120 120 to 160 160 to 200
75 (Option 2) 120 or 75 (Option 1) Not Used
* In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types. In CEPT mode, equalization is specified for coaxial or twisted-pair cable. Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0. Loss measured at 772 kHz. In 75 applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same transformer as in CEPT 120 applications (see Line Interface Unit: Line Circuitry section).
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Transmit (continued)
LIU Transmitter Configuration Modes
LIU Transmitter Zero Substitution Encoding (CODE) LIU transmitter zero substitution (B8ZS/HDB3) encoding can be activated only in the single-rail (DUAL = 0) system/framer interface mode. It is activated by setting CODE = 1 (register LIU_REG3, bit 2). Data transmitted from the framer interface on TPD-LIU will be B8ZS/ HDB3 encoded before appearing on TTIP and TRING at the line interface. LIU Transmitter Alarm Indication Signal Generator (XLAIS) When the transmit alarm indication signal control is set (XLAIS = 1) for a given channel (see register LIU_REG5, bit 1), a continuous stream of bipolar ones is transmitted to the line interface. The internal LIU to framer TPD interface (TPD) and internal LIU to framer TND interface (TND) signals are ignored during this mode. The XLAIS control is ignored when a remote loopback (RLOOP) is selected using loopback control bits LOOPA and LOOPB (register LIU_REG5, bits 2 to 3). The clock source used for the alarm indication signal is TLCK if present or INTSYSCK if TLCK is not present. The clock tolerance must meet the nominal transmission specifications of 1.544 MHz 32 ppm for DS1 (T1) or 2.048 MHz 50 ppm CEPT (E1). The XLAIS bit is defaulted to 1 on hardware reset allowing the transmitter to send AIS as soon as clocks are available, without needing to write the LIU registers*. Because the transmit equalization bits are needed to determine the correct system rate (DS1/E1), the reset default state of the equalization bits EQ2, EQ1, EQ0 (register LIU_REG6, bits 0--2) can be predetermined by setting the DS1_CEPT pin (see Table 7). The default transmit equalization is EQ2, EQ1, and EQ0 = 000 (0 dB T1/DS1) when DS1_CEPT = 1, and EQ2, EQ1, and EQ0 = 110 (CEPT 120 /75 ) when DS1_CEPT = 0. The transmit equalization bits can be subsequently programmed to any state by writing the LIU register regardless of the state of the DS1_CEPT pin. The DS1_CEPT pin is only used to determine the reset default state of the equalization bits.
LIU Transmitter Alarms
Loss of LIU Transmit Clock (LOTC) Alarm A loss of LIU transmit clock alarm (LOTC = 1, see register LIU_REG0, bit 3) is indicated if any of the clocks used in the LIU transmitter paths are absent. This includes loss of TLCK-LIU input, loss of RLCK-LIU during remote loopback, loss of jitter attenuator output clock (when enabled in transmit path), or the internal loss of clock from the pulse-width controller. For all of these conditions, the LIU transmitter timing clock is lost and no data can be driven onto the line. Output drivers TTIP and TRING are placed in a high-impedance state when this alarm is active. The LOTC alarm asserts between 3 s and 16 s after the clock is lost and deasserts immediately after detecting the first clock edge. The LOTC alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). Upon the transition from LOTC = 0 to LOTC = 1, an interrupt will be generated if the LOTC interrupt enable bit LOTCIE (register LIU_REG1, bit 3) is set. The reset default is LOTCIE = 0. An LOTC alarm may occur when RLOOP is activated and deactivated due to the phase transient that occurs as TLCK-LIU switches its source to and from RLCKLIU. Setting the RLOOP alarm prevention PRLALM = 1 (register LIU_REG4, bit 3) prevents the LOTC alarm from occurring at the activation and deactivation of RLOOP but allows the alarm to operate normally during the RLOOP active period. The reset default is PRLALM = 0. LIU Transmitter Driver Monitor (TDM) Alarm The transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit line transformer and periods of no data transmission. The TDM alarm (register LIU_REG0, bit 2) is the OR'd function of both faults and provides information about the integrity of the LIU transmitter signal path.
* If TLCK from the framer is present, automatic transmission of AIS upon reset will occur only if the CHI common control register FRM_PR45 bit 0 = 0, the default, or low-frequency PLLCK mode. In this case, PLLCK will be equal to the line transmit rate, either 1.544 MHz for DS1 or 2.048 MHz for CEPT.
Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Preliminary Data Sheet October 2000
Line Interface Unit: Transmit (continued)
The first monitoring function is provided to detect nonfunctional links and protect the LIU transmitter from damage. The alarm is set (TDM = 1) when one of the LIU transmitter line drivers (TTIP or TRING) is shorted to power supply or ground, or TTIP and TRING are shorted together. Under these conditions, internal circuitry protects the LIU transmitter from damage and excessive power supply current consumption by forcing the TTIP and TRING output drivers into a high-impedance state. The monitor detects faults on the transformer primary side, but the transformer secondary faults may not be detected. The monitor operates by comparing the line pulses with the transmit inputs. After 32 transmit clock cycles, the LIU transmitter is powered up in its normal operating mode. The LIU transmitter drivers attempt to correctly transmit the next data bit. If the error persists, TDM remains active to eliminate alarm chatter and the transmitter is again internally protected for another 32 transmit clock cycles. This process is repeated until the error condition is removed, and then the TDM alarm is deactivated. The TDM alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read).
The second monitoring function is to indicate periods of no data transmission. The alarm is set (TDM = 1) when 33 consecutive zeros have been transmitted. The alarm is cleared (TDM = 0) on the detection of a single pulse. This alarm condition does not alter the functionality of the signal path. Upon the transition from TDM = 0 to TDM = 1, a microprocessor interrupt will be generated if the TDM interrupt enable bit TDMIE (register LIU_REG1, bit 2) is set. The reset default is TDMIE = 0. A TDM alarm may occur when RLOOP is activated and deactivated. If the PRLALM bit is not set, then RLOOP may activate an LOTC alarm, which will put the output drivers TTIP and TRING in a high-impedance state as described in loss of LIU transmit clock (LOTC) alarm. The high-impedance state of the drivers may in turn generate a TDM alarm. Setting the HIGHZ alarm prevention PHIZALM = 1 (register LIU_REG4, bit 4) prevents the TDM alarm from occurring when the drivers are in a high-impedance state. The reset default is PHIZALM = 0.
DSX-1 Transmitter Pulse Template and Specifications
The DS1 pulse shape template is specified at the DSX (defined by CB119 and ANSI T1.102) and is illustrated in Figure 10. The LIU transmitter also meets the pulse template specified by ITU-T G.703 (not shown).
NORMALIZED AMPLITUDE (A)
1.0
0.5
0
-0.5 0 250 500 750 1000 1250 TIME (ns)
5-1160(F)
Figure 10. DSX-1 Isolated Pulse Template
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Transmit (continued)
Table 8. DSX-1 Pulse Template Corner Points (from CB119, T1.102) Maximum Curve UI -0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.25 0.93 1.16 ns 0 250 325 325 425 500 675 725 1100 1250 Normalized Amplitude 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 UI -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Minimum Curve ns 0 350 350 400 500 600 650 650 800 925 1100 1250 Normalized Amplitude -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
During DS1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in Table 9. Table 9. DS1 Transmitter Specifications Parameter Output Pulse Amplitude at DSX Output Pulse Width at Line Side of Transformer1 Output Pulse Width at Device Pins TTIP and TRING1 Positive/Negative Pulse Imbalance2 Power Levels:3,4 772 kHz 1.544 MHz5
1
Min 2.5 325 330 -- 12.6 29
Typ 3.0 350 350 0.1 -- 39
Max 3.5 375 370 0.4 17.9 --
Unit V ns ns dB dBm dB
Specification AT&T CB119, ANSI T1.102
1. With the line circuitry specified in Table 14. 2. Total power difference. 3. Measured in a 2 kHz band around the specified frequency. 4. Using Lucent transformer 2795B and components in Table 14. 5. Below the power at 772 kHz.
Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Transmit (continued)
CEPT Transmitter Pulse Template and Specifications
CEPT pulse shape template is specified at the system output (defined by ITU-T G.703) and is illustrated in Figure 11.
269 ns (244 + 25)
20%
10% V = 100% 10% 20% 194 ns (244 - 50) NOMINAL PULSE
50% 244 ns
219 ns (244 - 25) 10% 0% 10% 20% 10% 10%
488 ns (244 + 244)
5-3145(F)
Figure 11. ITU-T G.703 Pulse Template
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Line Interface Unit: Transmit (continued)
During E1 operation, the LIU transmitter TTIP and TRING pins will perform as specified in Table 10. Table 10. CEPT Transmitter Specifications Parameter Output Pulse 75 120 Output Pulse Width at Line Side of Transformer1 Output Pulse Width at Device Pins TTIP and TRING1 Positive/Negative Pulse Imbalance: Pulse Amplitude Pulse Width Zero Level (percentage of pulse amplitude) Return Loss:2 120 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Return Loss:2 75 51 kHz to 102 kHz 102 kHz to 3.072 MHz Amplitude1: Min 2.13 2.7 219 224 Typ 2.37 3.0 244 244 Max 2.61 3.3 269 264 Unit V V ns ns Specification ITU-T G.703
-4 -4 -5
1.5 1 0
4 4 5
% % % CH-PTT
9 15 11 7 9
-- -- -- -- --
-- -- -- -- --
dB dB dB dB dB ETS 300 166: 1993
1. With the line circuitry specified in Table 14, measured at the transformer secondary. 2. Using Lucent transformer 2795D or 2795C and components in Table 14.
Line Interface Unit: Jitter Attenuator
A selectable jitter attenuator is provided for narrowbandwidth jitter transfer function applications. When placed in the LIU receive path, the jitter attenuator provides narrow-bandwidth jitter filtering for line-synchronization. The jitter attenuator can also be placed in the LIU transmit path to provide clock smoothing for applications such as synchronous/asynchronous demultiplexers. In these applications, TLCK-LIU will have an instantaneous frequency that is higher than the data rate and some TLCK-LIU periods are suppressed (gapped) in order to set the average long-term TLCKLIU frequency to within the transmit line rate specification. The jitter attenuator will smooth the gapped clock.
Jitter Transfer Function
The jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. The jitter attenuator exhibits a single-pole roll-off (20 dB/decade) jitter transfer characteristic that has no peaking and a nominal filter corner frequency (3 dB bandwidth) of less than 4 Hz for DS1 operation and approximately 10 Hz for CEPT operation. Optionally, a lower bandwidth of approximately 1.25 Hz can be selected in CEPT operation by setting JABW0 = 1 (register LIU_REG4, bit 5) for systems desiring compliance with ETSI-TBR12 and TBR13 jitter attenuation requirements. The reset default is JABW0 = 0. For a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. Jitter amplitudes of less than approximately 0.2 UI will have greater attenuation than the single-pole roll-off characteristic. The jitter transfer curve is independent of data patterns. Typical jitter transfer curves of the jitter attenuator are given in Figures 13 and 15.
Generated (Intrinsic) Jitter
Generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. The jitter attenuator outputs a maximum of 0.04 UI peak-to-peak intrinsic jitter. Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Jitter Attenuator (continued)
Jitter Accommodation
The minimum jitter accommodation of the jitter attenuator occurs when the SYSCK frequency and the input clock's long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the LIU transmit path, the minimum accommodation is 28 UI peak-to-peak at the highest jitter frequency of 15 kHz. Typical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are given in Figures 12 and 14. When the jitter attenuator is placed in the data path, a difference between the SYSCK/16 frequency and the incoming line rate for receive applications, or the TCLK rate for transmit applications will result in degraded lowfrequency jitter accommodation performance. The peak-to-peak jitter accommodation (JApp) for frequencies from above the corner frequency of the jitter attenuator (Fc) to approximately 100 Hz is given by the following equation:
2 ( fsysclk - fdata )fdata JApp = 64 - ----------------------------------------------------------------- UI - 2fc
where: fdata = 1.544 MHz for DS1 or 2.048 MHz for E1, for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for E1, and for JABW0 = 1, fc = 1.25 Hz for E1, yfsysclk = SYSCK tolerance in ppm, yfdata = data tolerance in ppm. Note that for lower corner frequencies the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to 20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of 50 ppm.
Jitter Attenuator Enable (Transmit or Receive Path)
The jitter attenuator is placed in the LIU receive path by setting JAR = 1 (register LIU_REG3, bit 0). The jitter attenuator is selected in the LIU transmit path by setting JAT = 1 (register LIU_REG3, bit 1). When JAR = 1 and JAT = 1 or when JAR = 0 and JAT = 0, the jitter attenuator is disabled. Note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. The reset default case is JAR = JAT = 0.
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Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Jitter Attenuator (continued)
100 UI
28 UI
T1.408/I.431(DS1)/G.824(DS1)
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
10 UI
GR-499-CORE (NON-SONET CAT II INTERFACES)
I.431(DS1), G.824(DS1)
1.0 UI
TR-TSY-000009 (DS1, MUXes) GR-499/1244-CORE (CAT I INTERFACES)
0.1 UI
1
10
100
1k
10k
100k
FREQUENCY (Hz)
5-5264(F)
Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator
0
GR-253-CORE TR-TSY-000009
10
JITTER OUT/JITTER IN (dB)
20
30
40
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
50
60
1
10
100
1k
10 k
100 k
FREQUENCY (Hz)
5-5265(F)r.1
Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator Lucent Technologies Inc. Lucent Technologies Inc. 39
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Jitter Attenuator (continued)
100 UI G.823 37 UI
JABW0 = 1
JABW0 = 0
I.431(CEPT)/ETS-300-011
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION) 10 UI
G.823,ETS-300-011A1
1.0 UI
I.431(CEPT)/ETS-300-011
0.1 UI
1
10
100
1k
10k
100k
FREQUENCY (Hz)
5-5266(F)r.9
Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator
0
G.735-9 AT NATIONAL BOUNDARIES
I.431, G.735-9 WITH JITTER REDUCER
10
JITTER OUT/JITTER IN (dB)
ETSI-300-011 ETSI TBR12/13 20
30
TYPICAL (SUBJECT TO DEVICE CHARACTERIZATION)
JABW0 = 1
JABW0 = 0
40
50
60
1
10
100
1k
10 k
100 k
5-5267(Fr.1
FREQUENCY (Hz)
Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator 40 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Loopbacks
The LIU has independent loopback paths that are activated using LOOPA and LOOPB control bits (register LIU_REG5, bits 2 to 3) as shown in Table 10. The locations of these loopbacks are illustrated in Figure 5, Block Diagram of Line Interface Unit: Single Channel.
Table 11. Loopback Control Operation Normal1 Full Local Loopback Remote Loopback Symbol -- FLLOOP
2
LOOPA LOOPB 0 0 1 1 0 1 0 1
RLOOP3
Digital Local Loopback DLLOOP
Full Local Loopback (FLLOOP)
A full local loopback (FLLOOP) connects the LIU transmit driver input to the receive analog front-end circuitry. Valid transmit output data continues to be sent to the network. If the LIU transmitter AIS signal (all-ones signal) is sent to the network, by setting the XLAIS bit (register LIU_REG5, bit 1), the looped data is not affected. The ALOS alarm continues to monitor the receive line interface signal (RTIP and RRING) while the DLOS alarm monitors the looped data. See Digital Loss of Signal (DLOS) Alarm section on page 26 regarding the behavior of the DLOS alarm upon activation of FLLOOP .
1. The reset default condition is LOOPA = LOOPB = 0 (no loopback). 2. During the transmit AIS condition, the looped data will be the transmitted data from the framer or system interface and not the all ones signal. 3. Transmit AIS request is ignored.
Line Interface Unit: Other Features
LIU Powerdown (PWRDN)
Each LIU channel has an independent powerdown mode controlled by PWRDN (register LIU_REG5, bit 0). This provides power savings for systems which use backup channels. If PWRDN = 1, the corresponding LIU channel will be in a standby mode consuming only a small amount of power. It is recommended that the alarm registers for the powered down LIU channel be disabled by setting ALOSIE = DLOSIE = TDMIE = LOTCIE = 0 (register LIU_REG1, bits 0--3). If an LIU channel in powerdown mode needs to be placed back into service, the channel should be turned on (PWRDN = 0) approximately 5 ms before data is applied.
Remote Loopback (RLOOP)
A remote loopback (RLOOP) connects the recovered clock and retimed data to the LIU transmitter at the framer interface and sends the data back to the line. The LIU receiver front end, clock/data recovery, encoder/decoder (if enabled), jitter attenuator (if enabled), and LIU transmitter driver circuitry are all exercised during this loopback. The transmit clock, transmit data, and the transmit AIS inputs are ignored. Valid receive output data continues to be sent to RPDLIU and RND-LIU. This loopback mode is very helpful in isolating failures between systems. See Loss of LIU Transmit Clock (LOTC) Alarm section and LIU Transmitter Driver Monitor on page 33 regarding the behavior of the LOTC and TDM alarms upon activation and deactivation of RLOOP .
Loss of Framer Receive Line Clock (LOFRMRLCK Pin)
The LOFRMRLCK (pin 2/38) is set when the internal framer receive line clock is absent. During this alarm condition, the clock recovery and jitter attenuator functions are automatically disabled. If JAR = 1, the RLCKLIU, RPD-LIU, RND-LIU, and DLOS signals will be unknown.
Digital Local Loopback (DLLOOP)
A digital local loopback (DLLOOP) connects the transmit clock and data through the encoder/decoder pair to the receive clock and data output pins. This loopback is operational regardless of whether the encoder/decoder pair is enabled or disabled. The alarm indication signal can be transmitted (XLAIS = 1) without any effect on the looped signal. Lucent Technologies Inc. Lucent Technologies Inc.
In-Circuit Testing and Driver High-Impedance State (3-STATE)
If 3-STATE (pin 42/140) is activated (3-STATE = 0), the outputs TTIP, TRING, RDY_DTACK, INTERRUPT, and AD[7:0] are placed in a high-impedance state. The TTIP and TRING outputs have a limiting high-impedance capability of approximately 8 k.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Other Features
(continued)
Table 12. SYSCK (16x, CKSEL = 1) Timing Specifications Parameter Min Frequency DS1 CEPT Range*, Duty Cycle -- -- -100 40 Value Typ 24.704 32.768 -- -- Max -- -- 100 60 MHz MHz ppm % Unit
LIU Delay Values
The transmit coder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode. The remainder of the transmit path has 4.6 UI delay. The receive decoder has five UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode or CDR = 0. The equalizer plus slicer delay is nearly 0 UI delay. The jitter attenuator delay is nominally 33 UI but can be 2 UI-- 64 UI depending on state. The digital phase-locked loop used for timing recovery has 8 UI delay.
* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to 20 ppm in order to meet the jitter accommodation requirements of TBR12/ 13 as given in G.823 for line data rates of 50 ppm. If SYSCK is used as the source for AIS (see LIU Transmitter Alarm Indication Signal Generator (XLAIS)), it must meet the nominal transmission specifications of 1.544 MHz 32 ppm for DS1 (T1) or 2.048 MHz 50 ppm for CEPT (E1).
SYSCK Reference Clock
The LIU requires an externally applied clock, SYSCK pins 3 and 35, for the clock and data recovery function and the jitter attenuation option. SYSCK must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock such as from an external system oscillator or system clock for proper operation. It must not be derived from any recovered line clock (i.e., from RLCK or any synthesized frequency of RLCK). SYSCK may be supplied in one of two formats. The format is selected for each channel by CKSEL pins 48 and 133. For CKSEL = 1, a clock at 16x the primary line data rate clock (24.704 MHz for DS1 and 32.768 MHz for CEPT) is applied to SYSCK. For CKSEL = 0, a primary line data rate clock (1.544 MHz for DS1 and 2.048 MHz for CEPT) is applied to SYSCK. The CKSEL pin has an internal pull-up resistor allowing the pin to be left open, i.e., a no connect, in applications using a 16x reference clock and pulled down to ground for applications using a primary line data rate clock. 16x SYSCK Reference Clock The specifications for SYSCK using a 16x reference clock are defined in Table 12. The 16x reference clock is selected when CKSEL = 1.
Primary Line Rate SYSCK Reference Clock and Internal Reference Clock Synthesizer In some applications, it is more desirable to provide a reference clock at the primary data rate. In such cases, the LIU can utilize an internal 16x clock synthesizer allowing the SYSCK pin to accept a primary data rate clock. The specifications for SYSCK using a primary rate reference clock are defined in Table 13. Table 13. SYSCK (1x, CKSEL = 0) Timing Specifications Parameter Min Frequency DS1 CEPT Range*, Duty Cycle Rise and Fall Times (10%--90%) -- -- -100 40 -- Value Typ 1.544 2.048 -- -- -- Max -- -- 100 60 5 MHz MHz ppm % ns Unit
* When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on SYSCK should be tightened to 20 ppm in order to meet the jitter accommodation requirements of TBR12/ 13 as given in G.823 for line data rates of 50 ppm. If SYSCK is used as the source for AIS (see LIU Transmitter Alarm Indication Signal Generator (XLAIS)), it must meet the nominal transmission specifications of 1.544 MHz 32 ppm for DS1 (T1), or 2.048 MHz 50 ppm for CEPT (E1).
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
formed during this period. The device will be operational 2.7 ms after the deactivation of the hardware reset pin. Issuing an LIU software restart (LIU_REG2 bit 5 (RESTART) = 1) does not impact the clock synthesizer circuit.
SYSCK Reference Clock (continued)
The data rate reference clock and the internal clock synthesizer is selected when CKSEL = 0. In this mode, a valid and stable data rate reference clock must be applied to the SYSCK pin before and during the time a hardware reset is activated (RESET = 0). The reset must be held active for a minimum of two data rate clock periods to ensure proper resetting of the clock synthesizer circuit. Upon the deactivation of the reset pin (RESET = 1), the LIU will extend the reset condition internally for approximately 1/2(212 - 1) line clock periods, or 1.3 ms for DS1 and 1 ms for CEPT after the hardware reset pin has become inactive allowing the clock synthesizer additional time to settle. No activity such as microprocessor read/write should be per-
Line Interface Unit: Line Interface Networks
The transmit and receive tip and ring connections provide a matched interface to the line cable when used with a proper matching network. The diagram in Figure 16 shows the appropriate external components to interface to the cable for a single transmit/receive channel. The component values are summarized in Table 14, based on the specific application.
EQUIPMENT INTERFACE RECEIVE DATA ZEQ RP 1:N TRANSFORMER CC RR RR RS RRING DEVICE (1 CHANNEL) TRANSMIT DATA RL RT CP N:1
5-3693(F).d
RTIP
TTIP
RT
TRING
Figure 16. Line Termination Circuitry
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Line Interface Unit: Line Interface Networks (continued)
Table 14. Termination Components by Application1 Symbol Name DS12 Twisted Pair CC RP RR RS ZEQ RT RL N Center Tap Capacitor Receive Primary Impedance Receive Series Impedance Receive Secondary Impedance Equivalent Line Termination Tolerance Transmit Series Impedance Transmit Load Termination6 Transformer Turns Ratio 0.1 200 71.5 113 100 4 0 100 1.14 Cable Type CEPT 75 3 Coaxial Option 14 0.1 200 28.7 82.5 75 4 26.1 75 1.08 Option 25 0.1 200 59 102 75 4 15.4 75 1.36 CEPT 120 5 Twisted Pair 0.1 200 174 205 120 4 26.1 120 1.36 F Unit
% --
1. Resistor tolerances are 1%. Transformer turns ratio tolerances are 2%. 2. Use Lucent 2795B transformer. 3. For CEPT 75 applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 increases power dissipation by 13 mW per channel when driving 50% ones data. Option 2 allows for the use of the same transformer as in CEPT 120 applications. 4. Use Lucent 2795D transformer. 5. Use Lucent 2795C transformer. 6. A 5% tolerance is allowed for the transmit load termination.
The transmit and receive tip and ring connections should be provided with a matched and protected interface to the line (i.e., terminating impedance to match the characteristic impedance of the line cable and secondary line protection). For the purpose of line protection and matching network design, the equivalent input impedance of the receiver and the equivalent output circuit of the transmitter can be assumed to be as shown in Figure 17.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit: Line Interface Networks (continued)
20 k
3 pF RECEIVER INPUT* 47 k 2 pF
3 pF
20 k GRNDA
A. Receiver Input Approximate Equivalent Circuit
2 --2.5 TRANSMITTER OUTPUT 2 --2.5 PULSE VOLTAGE SOURCE
B. Transmitter Output Approximate Equivalent Circuit
5-6232(F).ar.5
* Approximately 0.3 V--2.0 V peak. Approximate pulse voltage source (peak).
Mode DS1 CEPT: 75 : Option 1 Option 2 120
Peak 3.0
Unit V
4.2 3.4 4.2
V V V
Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
LIU-Framer Interface
LIU-Framer Physical Interface
The transmit framer-LIU interface for the T7630 consists of the TND, TPD, and TLCK pins. In normal operations, TND, TPD, and TLCK are directly connected to the transmit line interface and the TPD, TND, and TLCK pins are driven from the transmit framer. The receive framer-LIU interface for the T7630 consists of the RPD, RND_BPV, and RLCK internal signals. In normal operations, RND, RPD, and RLCK are directly sourced from the internal receive line interface unit. In the framer mode, FRAMER = 0, the RPD, RND, and RLCK pins are directly connected to the receive framer (the internal receive line interface unit is bypassed). Figure 18 illustrates the interfaces of the transmit and receive framer units.
TRANSMIT HDLC FACILITY DATA LINK INTERFACE TLCK TPD TND TFDLCK TFDL
TTIP TRANSMIT LINE INTERFACE UNIT (XLIU)
TLCK TND TPD
TRING
TRANSMIT FRAMER (XFRMR)
RECEIVE CONCENTRATION HIGHWAY INTERFACE (RCHI)
RCHIDATA RCHIFS RCHICK
PLLCK RECEIVE HDLC FACILITY DATA LINK INTERFACE
RLCK
SYSTEM INTERFACE
LINE INTERFACE
RFDLCK RFDL RND_BPV RPD RTIP LIU_RLCK RECEIVE LINE LIU_RND/BPV INTERFACE LIU_RPD UNIT (RLIU) 0 FRM_RLCK FRM_RND RECEIVE FRAMER FRM_RPD (RFRMR) 1 TRANSMIT CONCENTRATION HIGHWAY INTERFACE (XCHI) TCHIDATA TCHICK TCHIFS
RRING
RFRMCK
FRAMER
5-4557(F).br.2
Figure 18. Block Diagram of Framer Line Interface
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
LIU-Framer Interface (continued)
Figure 19 shows the timing requirements for the transmit and receive framer interfaces in the LIU-bypass mode.
FRM_PR45 t1 PLLCK t2r-f t3 t2f-r t1-DS1 t1-CEPT HFLF = 0 648 ns 488 ns BIT 0 (HFLF) HFLF = 1 162 ns 122 ns
t2r-f: t2f-r: PLLCK TO TLCK DELAY = 50 ns t3-DS1 = 648 ns t3-CEPT = 488 ns
TLCK t4 TND, TPD t5-DS1 = 648 ns t5-CEPT = 488 ns t4 = TLCK TO VALID TPD, TND = 30 ns
t5 RLCK
t6 = RPD, RND SETUP TO RISING RLCK = 40 ns t6 RND, RPD t8 RFRMCK
5-4558(F).cr.3
t7
t7 = RPD, RND HOLD FROM RISING RLCK = 40 ns
t8r-f: t8f-r: RLCK TO RFRMCK DELAY = 50 ns
Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing
Interface Mode and Line Encoding
Single Rail The default mode for the LIU-framer interface is singlerail, register LIU_REG3 bit 3 (DUAL) = 0 and register FRM_PR8 bit 7 = 1, bit 6 = 1, and bit 5 = 0. In the single-rail terminator mode (FRAMER = 1), the LIU bipolar encoder and decoder may be enabled by setting register LIU_REG3 bit 2 (CODE) to 1. Signals passed on the internal LIU-framer interface are data (LIU_RPD and TPD), clock (LIU_RLCK and TLCK), and received bipolar violations (LIU_RND/BPV). When LIU_RND/BPV = 1, the BPV counter increments by one on the rising edge of LIU_RLCK. In the single-rail framer mode (FRAMER = 0), external signals to and from the framer are data (RTIP_RPD, pin 11/27 and TPD, pin 44/138), clock (RLCK, pin 47/135 and TLCK, pin 46/136), and received bipolar violations (RRING_RND, pin 10/28). When RRING_RND = 1, the BPV counter increments by one on the rising edge of RLCK. In this mode, TND (pin 45/137) is forced to the 0 state. Lucent Technologies Inc. Lucent Technologies Inc.
Dual Rail Dual-rail LIU-framer interface mode is selected by setting LIU_REG3 bit 3 (DUAL) = 1 and by selecting one of the dual-rail framer modes of FRM_PR8 bit 5--bit 7. In the dual-rail terminator mode (FRAMER = 1), the framer bipolar encoder and decoder are enabled. Signals passed on the internal LIU-framer interface are data (LIU_RPD, LIU_RND, TPD, and TND), and clock (LIU_RLCK and TLCK). When bipolar violations are detected by the framer, the BPV counter increments by one on the rising edge of LIU_RLCK. In the dual-rail framer mode (FRAMER = 0), external signals to and from the framer are data (RTIP_RPD, pin 11/27; RRING_RND, pin 10/28; TPD, pin 44/138; and TND, pin 45/137) and clock (RLCK, pin 47/135 and TLCK, pin 46/136). When bipolar violations are detected by the framer, the BPV counter increments by one on the rising edge of RLCK.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
LIU-Framer Interface (continued)
DS1: Alternate Mark Inversion (AMI)
The default line code used for T1 is alternate mark inversion (AMI). The coding scheme represents a one with a pulse (mark) on the positive or negative rail and a zero with no pulse on either rail. This scheme is shown in Table 15. Table 15. AMI Encoding Input Bit Stream AMI Data 1011 -0+- 0000 0000 0111 0+-+ 1010 -0+0
The T1 ones density rule states that: In every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively [AT&T TR62411 (1988), ANSI T1.231 (1997)]. Receive ones density is monitored by the receive line interface as per T1M1.3/93-005, ITU G.775, or TR-TSY000009. The receive framer indicates excessive zeros upon detecting any zero string length greater than 15 contiguous zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.
DS1: Zero Code Suppression (ZCS)
Zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed with a one. The line format (shown in Table 16) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. The default ZCS format stuffs the seventh bit of those ALL-ZERO time slots programmed for robbed-bit signaling (as defined in the signaling control registers with the F and G bits). The receive framer indicates excessive zeros upon detecting any zero string length greater than fifteen contiguous zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations. Table 16. DS1 ZCS Encoding Input Bit Stream ZCS Data (Framer Mode) T7630 Default ZCS 00000000 00000010 00000010 01010000 01010010 01010000 00000000 00000010 00000000 (data time slot remains clear) 00000000 00000010 00000010
DS1: Binary 8 Zero Code Suppression (B8ZS) Clear channel transmission can be accomplished using Binary 8 Zero Code Suppression (B8ZS). Eight consecutive zeros are replaced with the B8ZS code. This code consists of two bipolar violations in bit positions four and seven and valid bipolar marks in bit positions five and eight. The receiving end recognizes this code and replaces it with the original string of eight zeros. The receive framer indicates excessive zeros upon detecting a block of eight or more consecutive zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
LIU-Framer Interface (continued)
Table 17 shows the encoding of a string of zeros using B8ZS. B8ZS is recommended when ESF format is used. V represents a violation of the bipolar rule, and B represents an inserted pulse conforming to the AMI rule. Table 17. DS1 B8ZS Encoding Bit Positions Before B8ZS After B8ZS 1 0 0 2 0 0 3 0 0 4 0 V 5 0 B 6 0 0 7 0 V 8 0 B -- 1 B -- 0 0 -- 1 B 1 0 0 2 0 0 3 0 0 4 0 V 5 0 B 6 0 0 7 0 V 8 0 B
CEPT: High-Density Bipolar of Order 3 (HDB3)
The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). HDB3 uses a substitution code that acts on strings of four zeros. The substitute HDB3 codes are 000V and B00V, where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule defined in ITU Rec. G.701, item 9004. The choice of the B00V or 000V is made so that the number of B pulses between consecutive V pulses is odd. In other words, successive V pulses are of alternate polarity so that no direct current (dc) component is introduced. The substitute codes follow each other if the string of zeros continues. The choice of the first substitute code is arbitrary. A line code error consists of two pulses of the same polarity that is not defined as one of the two substitute codes. Excessive zeros consist of any zero string length greater than four contiguous zeros. Both excessive zeros and coding violations are indicated as bipolar violations. An example is shown in Table 18. Table 18. ITU HDB3 Coding Input Bit Stream HDB3-coded Data HDB3-coded Levels HDB3 with 5 Double BPVs 1011 1011 -0+- -0+- 0000 000V 000- -000 1-BPV 01 01 0+ 0+ 0000 000V 000+ +00+ 3-BPV 0000 B00V -00- 0-- - 5-BPV 0000 B00V +00+ +00+ 0000 B00V -00- -00-
Frame Formats
The supported North American T1 framing formats are superframe (D4, SLC-96, and digital data service-DDS) and extended superframe (ESF). The device can be programmed to support the ITU-CEPT-E1 basic format with and without CRC-4 multiframe formatting. This section describes these framing formats.
T1 Framing Structures
T1 is a digital transmission system which multiplexes twenty-four 64 kbits/s time slots (DS0) onto a serial link. The T1 system is the lowest level of hierarchy on the North American T-carrier system, as shown in Figure 20. Table 19. T-Carrier Hierarchy T Carrier DS0 Channels Bit Rate (Mbits/s) 1.544 3.152 6.312 44.736 274.176 Digital Signal Level DS1 DS1C DS2 DS3 DS4 49
T1 24 T1-C 48 T2 96 T3 672 T4 4032 Lucent Technologies Inc. Lucent Technologies Inc.
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
Frame, Superframe, and Extended Superframe Definitions Each time slot (DS0) is an assembly of 8 bits sampled every 125 s. The data rate is 64 kbits/s and the sample rate is 8 kHz. Time-division multiplexing 24 DS0 time slots together produces a 192-bit (24 DSzeros) frame. A framing bit is added to the beginning of each frame to allow for detection of frame boundaries and the transport of additional maintenance information. This 193-bit frame, also referred to as a DS1 frame, is repeated every 125 s to yield the 1.544 Mbits/s T1 data rate. DS1 frames are bundled together to form superframes or extended superframes.
FRAME 1
FRAME 2
FRAME 3
FRAME 23
FRAME 24
24-FRAME EXTENDED SUPERFRAME ESF = 3.0 ms
FRAME 1
FRAME 2
FRAME 11
FRAME 12
12-FRAME SUPERFRAME SF = 1.5 ms
F BIT
TIME SLOT 1
TIME SLOT 2
TIME SLOT 24
193-bit FRAME DS1 = 125 s
1
2
3
4
5
6
7
8
8-bit TIME SLOT DS0 = 5.19 s
5-4559(F).br.1
Figure 20. T1 Frame Structure Transparent Framing Format The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (FRM_PR43 bits 2--0 must be set to 000) and either transparent framing mode one or transparent framing mode two is enabled (FRM_PR26 bit 3 or bit 4 must be set to 1). In transparent mode one or mode two, the transmit framer extracts from the receive system data bit 8 of time slot 1 and inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot 1 are ignored by the transmit framer. The receive framer will extract the f-bit (or 193rd bit) of the receive line data and insert it into bit 7 of time slot one of the system data; the other bits of time slot 1 are set to 0. Frame integrity is maintained in both the transmit and receive framer sections.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT CHI FRAME
(STUFF TIME SLOT) 0 0 0 0 0 0 0 F BIT
F BIT TIME SLOT 1 TIME SLOT 2
TIME SLOT 24
TRAMSMIT FRAMER'S 193-bit FRAME DS1 = 125 s
5-5989(F).ar.1
Figure 21. T1 Transparent Frame Structure In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The remaining bits in time slot 1 are set to zero.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
D4 Frame Format D4 superframe format consists of 12 DS1 frames. Table 20 shows the structure of the D4 superframe. Table 20. D4 Superframe Format Frame Number1 Framing Bits Bit Terminal Signal Number2 Frame FT Frame FS 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 1 -- 0 -- 1 -- 0 -- 1 -- 0 -- -- 0 -- 0 -- 1 -- 1 -- 1 -- 0 Bit Used in Each Time Slot Traffic (All Channels) 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 Signaling Options
Remote Signaling None4 2-State 4-State Alarm3 2 2 2 2 2 2 2 2 2 2 2 2 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- B
1 2 3 4 5 65 7 8 9 10 11 125
1. Frame 1 is transmitted first. 2. Following ANSI T1.403, the bits are numbered 0--2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit 1 of each DS0 is transmitted first. 3. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number 2123) to a 1-state when enabled. 4. Signaling option none uses bit 8 for traffic data. 5. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.
The receive framer uses both the FT and FS framing bits during its frame alignment procedure. Digital Data Service (DDS) Frame Format The superframe format for DDS is the same as that given for D4. DDS is intended to be used for data-only traffic, and as such, the system should ensure that the framer is in the nonsignaling mode. DDS uses time slot 24 (FAS channel) to transmit the remote frame alarm and data link bits. The format for time slot 24 is shown in Table 21. The facility data link timing is shown in Figure 22 below. Table 21. DDS Channel-24 Format Time Slot 24 = 10111YD0 Y = (bit 6) Remote frame alarm: 1 = no alarm state; 0 = alarm state D = (bit 7) Data link bits (8 kbits/s)
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
t8 TFDLCK t8: TFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES) t9 t9
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
RFDLCK
t10: RFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES)
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).cr.1
Figure 22. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections
SLC-96 Frame Format SLC-96 superframe format consists of 12 DS1 frames similar to D4. The FT pattern is exactly the same as D4. The Fs pattern uses that same structure as D4 but also incorporates a 24-bit data link word as shown below.
SLC-96 24-bit DATA LINK WORD
Fs =
. . . 000111000111D1DDDDDDDDDDDDDDDDDDDDDDD24000111000111DDD . . .
FRAME N -1 FRAME FRAME N N+1 FRAME N+2 FRAME N+3 FRAME N+4 FRAME N+5 FRAME FRAME FRAME N+6 N+7 N+8
SLC-96 36-FRAME D-bit SUPERFRAME INTERVAL (72 DS1 FRAMES)
5-6421(F)r.1
Figure 23. Fs Pattern SLC-96 Superframe Format
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
External TFDL Source. Data may be inserted and extracted from the SLC-96 data link from either the external facility data link (TFDL) ports or the SLC-96 data stack. Source selection is controlled by FRM_PR21 bit 6 and FRM_PR29 bit 5--bit 7. The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this pattern. When sourcing an external bit stream, it is the system's responsibility to ensure that TFDL data contain the pattern of 000111000111 . . . . The D pattern sequence is shown in Table 22. Table 23 shows the encoding for the line switch field. Table 22. SLC-96 Data Link Block Format Data Link Block D1 (leftmost bit) D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 (rightmost bit) Bit Definition C1--concentrator bit C2--concentrator bit C3--concentrator bit C4--concentrator bit C5--concentrator bit C6--concentrator bit C7--concentrator bit C8--concentrator bit C9--concentrator bit C10--concentrator bit C11--concentrator bit Spoiler bit 1 Spoiler bit 2 Spoiler bit 3 M1--maintenance bit M2--maintenance bit M3--maintenance bit A1--alarm bit A2--alarm bit S1--line-switch bit S2--line-switch bit S3--line-switch bit S4--line-switch bit Spoiler bit 4 Bit Value 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Defined in Table 23 Defined in Table 23 Defined in Table 23 Defined in Table 23 1
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Frame Formats (continued)
Table 23. SLC-96 Line Switch Message Codes S1 1 1 1 1 1 0 0 0 S2 1 1 1 1 0 1 1 0 S3 1 1 0 0 1 0 0 1 S4 1 0 1 0 0 1 0 0 Code Definition Idle Switch line A receive Switch line B transmit Switch line C transmit Switch line D transmit Switch line B transmit and receive Switch line B transmit and receive Switch line B transmit and receive
Internal SLC-96 Stack Source. Optionally, a SLC-96 FDL stack may be used to insert and correspondingly extract the FDL information in the SLC-96 frame format. The transmit SLC-96 FDL bits are sourced from the transmit framer SLC-96 FDL stack. The SLC-96 FDL stack (see FRM_PR31--FRM_PR35) consists of five 8-bit registers that contain the SLC-96 FS and D-bit information as shown in Table 24. The transmit stack data is transmitted to the line when the stack enable mode is active in the parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5--bit 7 = x10 (binary). The receive SLC-96 stack data is received when the receive framer is in the superframe alignment state. In the SLC-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC-96 stack is halted and neither the receive stack interrupt nor receive stack flag are asserted. Table 24. Transmit and Receive SLC-96 Stack Structure Register Number 1 (LSR) 2 3 4 5 Bit 7 (MSB) 0 0 C1 C9 M3 Bit 6 0 0 C2 C10 A1 Bit 5 0 0 C3 C11 A2 Bit 4 Bit 3 Bit 2 Bit 1 1 1 C7 M1 S4 Bit 0 (LSB) 1 1 C8 M2 SPB4 = 1
0 0 1 0 0 1 C4 C5 C6 SPB1 = 0 SPB2 = 1 SPB3 = 0 S1 S2 S3
Bit 5--bit 0 of the first 2 bytes of the SLC-96 FDL stack in Table 24 are transmitted to the line as the SLC-96 FS sequence. Bit 7 of the third stack register is transmitted as the C1 bit of the SLC-96 D sequence. The spoiler bits (SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC-96 stack information for the transmit and receive framer is described below. The transmit SLC-96 stack must be written with valid data when transmitting stack data. The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (SLC96 transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the stack during this interval will be transmitted during the next SLC-96 superframe D-bit interval. By reading bit 5 in register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack is not updated, then the content of Lucent Technologies Inc. Lucent Technologies Inc.
the stack is retransmitted to the line. The start of the SLC-96 36-frame FS interval of the transmit framer is a function of the first 2 bytes of the SLC-96 transmit stack registers. These bytes must be programmed as shown in Table 24. Programming any other state into these two registers disables the proper transmission of the SLC-96 D bits. Once programmed correctly, the transmit SLC-96 D-bit stack is transmitted synchronous to the transmit SLC-96 superframe structure. On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54--FRM_SR58) by setting bit 4 in register FRM_SR4 (SLC-96 receive FDL stack ready) high. The system then has about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained above, the SLC-96 receive stack is not updated when superframe alignment is lost. 55
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
Extended Superframe Format The extended superframe format consists of 24 DS1 frames. The F bits are used for frame alignment, superframe alignment, error checking, and facility data link transport. Table 25 shows the ESF frame format. Table 25. Extended Superframe (ESF) Structure
Frame Number1 Frame Bit Bit Use in Each Time Slot Signaling Option2
Bit Number3
1 2 3 4 5 66 7 8 9 10 11 126 13 14 15 16 17 186 19 20 21 22 23 246 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 2316 2509 2702 2895 3088 3281 3474 3667 3860 4053 4246 4439
FE
-- -- -- 0 -- -- -- 0 -- -- -- 1 -- -- -- 0 -- -- -- 1 -- -- -- 1
DL
D -- D -- D -- D -- D -- D -- D -- D -- D -- D -- D -- D --
CRC64
-- C1 -- -- -- C2 -- -- -- C3 -- -- -- C4 -- -- -- C5 -- -- -- C6 -- --
Traffic
1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7
Signaling None
5
2-State
-- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A
4-State
-- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- A -- -- -- -- -- B
16-State
-- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- C -- -- -- -- -- D
-- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1. Frame 1 is transmitted first. 2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled. 3. Following ANSI T1.403, the bits are numbered 0--4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit 1 of each DS0 is transmitted first. 4. The C1 to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe. 5. Signaling option none uses bit 8 for traffic data. 6. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.
The ESF format allows for in-service error detection and diagnostics on T1 circuits. ESF format consist of 24 framing bits: six for framing synchronization (2 kbits/s); six for error detection (2 kbits/s); and 12 for in-service monitoring and diagnostics (4 kbits/s).
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
Cyclic redundancy checking is performed over the entire ESF data payload (4,608 data bits, with all 24 framing bits (FE, DL, CRC-6) set to one during calculations). The CRC-6 bits transmitted in ESF will be determined as follows:
s
The check bits, c1 through c6, contained in ESF(n + 1) will always be those associated with the contents of ESF(n), the immediately preceding ESF. When there is no ESF immediately preceding, the check bits may be assigned any value. For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way. The resulting 4632 bits of ESF(n) are used, in order of occurrence, to construct a polynomial in x such that the first bit of ESF(n) is the coefficient of the term x4631 and the last bit of ESF(n) is the coefficient of the term x0. The polynomial is multiplied by the factor x6, and the result is divided, modulo 2, by the generator polynomial x6 + x + 1. The coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of check bits, c1 through c6, that are transmitted in ESF(n + 1). The ordering is such that the coefficient of the term x5 in the remainder polynomial is check bit c1 and the coefficient of the term x0 in the remainder polynomial is check bit c6.
s s
s
The ESF remote frame alarm consists of a repeated eight ones followed by eight zeros transmitted in the data link position of the framing bits.
T1 Loss of Frame Alignment (LFA)
Loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability of the receive framer to maintain the proper sequence of frame bits. The number of errored framing bits required to detect a loss of frame alignment is given is Table 26. Table 26. T1 Loss of Frame Alignment Criteria Format D4 Number of Errored Framing Bits That Will Cause a Loss of Frame Alignment Condition 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. 2 errored FE bits out of 4 consecutive FE bits or optionally 320 or more CRC-6 errored checksums within a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.
SLC-96
DDS: Frame ESF
The receive framer indicates the loss of frame and superframe conditions by setting the LFA and LSFA bits (FRM_SR1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. The local system may give indication of its LFA state to the remote end by transmitting a remote frame alarm (RFA). In addition, in the LFA state, the system may transmit an alarm indication signal (AIS) to the system interface.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
T1 Frame Recovery Alignment Algorithms
When in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its internal circuitry to this new alignment. The receive framer's synchronization circuit inhibits realignment in T1 framing formats when repetitive data patterns emulate the T1 frame alignment patterns. T1 frame synchronization will not occur until all frame sequence emulating patterns disappear and only one valid pattern exists. The loss of frame alignment state will always force a loss of superframe alignment state. Superframe alignment is established only after frame alignment has been determined in the D4 and SLC-96 frame format. Table 27 gives the requirements for establishing T1 frame and superframe alignment. Table 27. T1 Frame Alignment Procedures Frame Format D4: Frame Alignment Procedure Using the FT frame position as the starting point, frame alignment is established when 24 consecutive FT and FS frame bits, excluding the twelfth FS bit, (48 total frames) are received error-free. Once frame alignment is established, then superframe alignment is determined. After frame alignment is determined, two valid superframe bit sequences using the FS bits must be received error-free to establish superframe alignment. Using the FT frame position as the starting point, frame alignment is established when 24 consecutive FT frame bits (48 total frames) are received error-free. Once frame alignment is established, then superframe alignment is determined. After frame alignment is determined, superframe alignment is established on the first valid superframe bit sequence 000111000111. Using the FT frame position as the starting point, frame alignment is established when six consecutive FT/FS frame bits and the DDS FAS in time slot 24 are received error-free. In the DDS format, there is no search for a superframe structure. Frame and superframe alignment is established simultaneously using the FE framing bit. Alignment is established when 24 consecutive FE bits are received errorfree. Once frame/superframe alignment is established, the CRC-6 receive monitor is enabled.
D4: Superframe
SLC-96: Frame
SLC-96: Superframe
DDS: Frame
ESF
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
T1 Robbed-Bit Signaling
To enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0. Robbed-bit signaling, used in either ESF or SF framing formats, robs the eighth bit of the voice channels of every sixth frame. The signaling bits are designated A, B, C, and D, depending on the signaling format used. The robbedbit signaling format used is defined by the state of the F and G bits in the signaling registers (see DS1: Robbed-Bit Signaling). The received channel robbed-bit signaling format is defined by the corresponding transmit signaling F and G bits. Table 28 shows the state of the transmitted signaling bits as a function of the F and G bits. Table 28. Robbed-Bit Signaling Options G 0 0 1 1 F 0 1 0 1 Robbed-Bit Signaling Format 6 ESF: 16-State SLC*: 9-State, 16-State 4-State Data channel (no signaling) 2-State A A Frame 12 B 18 C 24 D
B A B PAYLOAD DATA A A A A
* See register FRM_PR43 bit 3 and bit 4.
The robbed-bit signaling format for each of the 24 T1 transmit channels is programmed on a per-channel basis by setting the F and G bits in the transmit signaling direction.
SLC-96 9-State Signaling SLC-96 9-state signaling state is enabled by setting both the F and G bits in the signaling registers to the 0 state, setting the SLC-96 signaling control register FRM_PR43 bit 3 to 1, and setting register FRM_PR44 bit 0 to 0. Table 29 shows the state of the transmitted signaling bits to the line as a function of the A, B, C and D bit settings in the transmit signaling registers. In Table 29 below, X indicates either a 1 or a 0 state, and T indicates a toggle, transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit.
In the line receive direction, this signaling mode functions identically to the preceding transmit path description. Table 29. SLC-96 9-State Signaling Format Transmit Signaling Register Settings Transmit to the Line Signal Bits C 0 0 0 1 1 1 X X X D 0 1 X 0 1 X 0 1 X A = f(A,C) 0 0 0 T T T 1 1 1 B = f(B,D) 0 T 1 0 T 1 0 T 1
SLC-96 Signaling States
State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9
A 0 0 0 0 0 0 1 1 1
B 0 0 1 0 0 1 0 0 1
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
16-State Signaling The default signaling mode while in SLC-96 framing is 16-state signaling. SLC-96 16-state signaling is enabled by setting both the F and G bits in the signaling registers to the 0 state, setting the SLC-96 signaling control register FRM_PR43 bit 3 and bit 4 to 0, and setting register FRM_PR44 bit 0 to 0. Table 30 shows the state of the transmitted signaling bits to the line as a function of the A, B, C, and D bit settings in the transmit signaling registers. In Table 30 below, under Transmit to the Line Signal Bits, A and B are transmitted into one SLC-96 12-frame signaling superframe, while A' and B' are transmitted into the next successive SLC-96 12-frame signaling superframe. In the line receive direction, this signaling mode functions identically to the preceding transmit path description. The signaling mapping of this 16-state signaling mode is equivalent to the mapping of the SLC-96 9-state signaling mode. Table 30. 16-State Signaling Format Transmit Signaling Register Settings Transmit to the Line Signal Bits D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A' 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B' 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SLC-96 Signaling States
State 0 State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures
As defined in ITU Rec. G.704, the CEPT 2.048 frame, CRC-4 multiframe, and channel associated signaling multiframe structures are illustrated in Figure 24.
CRC-4 MULTIFRAME IN TIME SLOT 0 FRAME 0 OF CRC-4 MULTIFRAME
0000
X0 YM X1 X2
A1 B1 C1 D1 A16 B16 C16 D16 C1 0 01 C2 0 01 C3 0 11 C4 0 01 C1 0 11 C2 0 11 C3 0 E1 C4 0 E1 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 A2 B2 C2 D2 A17 B17 C17 D17 A3 B3 C3 D3 A18 B18 C18 D18 A4 B4 C4 D4 A19 B19 C19 D19 A5 B5 C5 D5 A20 B20 C20 D20 A6 B6 C6 D6 A21 B21 C21 D21 A7 B7 C7 D7 A22 B22 C22 D22 A8 B8 C8 D8 A23 B23 C23 D23 A9 B9 C9 D9 A24 B24 C24 D24 A10 B10 C10 D10 A25 B25 C25 D25 A11 B11 C11 D11 A26 B26 C26 D26 A12 B12 C12 D12 A27 B27 C27 D27 A13 B13 C13 D13 A28 B28 C28 D28 FRAME 15 OF CRC-4 MULTIFRAME A14 B14 C14 D14 A29 B29 C29 D29 A15 B15 C15 D15 A30 B30 C30 D30 CHANNEL ASSOCIATED SIGNALING MULTIFRAME IN TIME SLOT 16
FRAME 0 TIME SLOT 16 MULTIFRAME
FRAME 15 TIME SLOT 16 MULTIFRAME
CHANNEL NUMBERS REFER TO TELEPHONE CHANNEL NUMBERS. TIME SLOTS 1 TO 15 AND 17 TO 31 ARE ASSIGNED TO TELEPHONE CHANNELS NUMBERED FROM 1 TO 30.
Si 0 0
1
1
0
1
1
TIME SLOT 1
TIME SLOT 31
FAS FRAME PRIMARY BASIC FRAME STRUCTURE
Si 1 A SA4 SA5 SA6 SA7 SA8
TIME SLOT 1
TIME SLOT 31
NOT FAS FRAME
TIME SLOT 0
TIME SLOT 1
TIME SLOT 16
TIME SLOT 31
256-bit FRAME = 125 s
12
34
56
78
8-bit TIME SLOT = 3.90625 s
5-4548(F).cr.1
Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe Structures
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Frame Formats (continued)
CEPT 2.048 Basic Frame Structure
The ITU Rec. G.704 Section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. The frame repetition rate is 8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in Table 31. Table 31. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame Basic Frames Frame Alignment Signal (FAS) Not Frame Alignment Signal (NOT FAS) Bit 1 (MSB) Si Si Bit 2 0 1 Bit 3 0 A Bit 4 1 Sa4 Bit 5 1 Sa5 Bit 6 0 Sa6 Bit 7 1 Sa7 Bit 8 (LSB) 1 Sa8
The function of each bit in Table 31 is described below:
s
The Si bits are reserved for international use. A specific use for these bits is described in Table 32. If no use is realized, these bits should be fixed at one on digital paths crossing an international border. Bit 2 of the NOT FAS frames is fixed to one to assist in avoiding simulations of the frame alignment signal. Bit 3 of the NOT FAS is the remote alarm indication (A bit). In undisturbed operation, this bit is set to 0; in alarm condition, set to one. Bits 4--8 of the NOT FAS (Sa4--Sa8) may be recommended by ITU for use in specific point-to-point applications. Bit Sa4 may be used as a messagebased data link for operations, maintenance, and performance monitoring. If the data link is accessed at intermediate points with consequent alterations to the Sa4 bit, the CRC-4 bits must be updated to retain the correct end-to-end path termination functions associated with the CRC-4 procedure. The receive framer does not implement the CRC-4 modifying
algorithm described in TU Rec. G.706 Annex C. Bits Sa4--Sa8, where these are not used, should be set to one on links crossing an international border.
s s
MSB = most significant bit and is transmitted first. LSB = least significant bit and is transmitted last.
s
Transparent Framing Format The transmit framer can be programmed to transparently transmit 256 bits of system data to the line. The transmit framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Framer Reset and Transparent Mode Control Register (FRM_PR26) on page 174). In transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the RCHI payload unmodified to the line. Time slot 1 of the RCHI, determined by the RCHIFS signal, is inserted into the FAS/NOTFAS time slot of the transmit line interface. Frame integrity is maintained in both the transmit and receive framer sections.
s
s
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT CHI FRAME
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT LINE FRAME
5-5988(F)
Figure 25. CEPT Transparent Frame Structure In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The entire receive line payload is transmitted unmodified to the CHI. In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitoring of receive line data is performed and data is transmitted to the CHI as programmed. 62 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
CEPT Loss of Basic Frame Alignment (LFA)
Frame alignment is assumed to be lost when:
s
If CRC-4 is enabled, loss of CRC-4 multiframe alignment is forced. If CRC-4 is enabled, the monitoring and processing of CRC-4 checksum errors is halted. If CRC-4 is enabled, all monitoring and processing of received E-bit information is halted. If CRC-4 is enabled, the receive continuous E-bit alarm is deactivated. If CRC-4 is enabled, optionally, E bit = 0 is transmitted to the line for the duration of loss of CRC-4 multiframe alignment if register FRM_PR28 bit 4 is set to 1. If time slot 16 signaling is enabled, loss of the signaling multiframe alignment is forced. If time slot 16 signaling is enabled, updating of the signaling data is halted.
s
s s
As described in ITU Rec. G.706 Section 4.1.1, three consecutive incorrect frame alignment signals have been received. So as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in NOT FAS frames have been received with an error on three consecutive occasions. Optionally, as described in ITU Rec. G.706 Section 4.3.2, by exceeding a count of >914 errored CRC-4 blocks out of 1000, with the understanding that a count of 915 errored CRC blocks indicates false frame alignment. On demand via the control registers.
s
s
s
s
s
s
s
In the LFA state:
s s
No additional FAS or NOT FAS errors are processed. The received remote frame alarm (received A bit) is deactivated. All NOT-FAS bit (Si bit, A bit, and Sa4 to Sa8 bits) processing is halted. Receive Sa6 status bits are set to 0. Receive Sa6 code monitoring and counting is halted. All receive Sa stack data updates are halted. The receive Sa stack ready, register FRM_SR4 bit 6 and bit 7, is set to 0. If enabled, the receive Sa stack interrupt bit is set to 0. Receive data link (RFDL) is set to 1 and RFDCLK maintains previous alignment. Optionally, the remote alarm indication (A = 1) may be automatically transmitted to the line if register FRM_PR27 bit 0 is set to 1. Optionally, the alarm indication signal (AIS) may be automatically transmitted to the system if register FRM_PR19 bit 0 is set to 1.
CEPT Loss of Frame Alignment Recovery Algorithm
The receive framer begins the search for basic frame alignment one bit position beyond the position where the LFA state was detected. As defined in ITU Rec. G.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected:
s
s
s s s
For the first time, the presence of the correct frame alignment signal in frame n. The absence of the frame alignment signal in the following frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. For the second time, the presence of the correct frame alignment in the next frame, n + 2.
s
s
s
s
Failure to meet the second or third bullet above will initiate a new basic frame search in frame n + 2.
s
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
CEPT Time Slot 0 CRC-4 Multiframe Structure
The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy check-4 (CRC-4) procedure as detailed below. The allocation of bits 1--8 of time slot 0 of every frame is shown in Table 32 for the complete CRC-4 multiframe. Table 32. ITU CRC-4 Multiframe Structure Multiframe Submultiframe (SMF) I Frame Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bits 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E C4 E 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8
II
Notes: C1 to C4 = cyclic redundancy check-4 (CRC-4) bits. E = CRC-4 error indication bits. Sa4 to Sa8 = spare bits. A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.
The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes (SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multiframe structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment signal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received errored submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The received E bits will always be taken into account, by the receive E-bit processor*, even when the SMF that contains them is found to be errored. In the case where there exists equipment that does not use the E bits, the state of the E bits should be set to a binary 1 state.
* The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomial x4 + x + 1, of the polynomial representation of the submultiframe N - 1. Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. Similarly, C1 is defined to be the most significant bit of the remainder and C4 the least significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.2, follows:
s
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)
Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search for CRC-4 multiframe alignment is initiated. During a loss of CRC-4 multiframe alignment state:
s s
The CRC-4 error counter is halted. The CRC-4 error monitoring circuit for errored seconds and severely errored seconds is halted. The received E-bit counter is halted. The received E-bit monitoring circuit for errored seconds and severely errored seconds at the remote end interface is halted. Receive continuous E-bit monitoring is halted. All receive Sa6 code monitoring and counting functions are halted. The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated. Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1. Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1. Optionally, if LTS0MFA monitoring in the performance counters is enabled, by setting registers FRM_PR14 through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the LTS0MFA state.
s s
The CRC-4 bits in the SMF are replaced by binary zeros. The SMF is then acted upon the multiplication/division process referred to above. The remainder resulting from the multiplication/division process is stored, ready for insertion into the respective CRC-4 locations of the next SMF.
s
s s
s
The decoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.3, follows:
s
s
A received SMF is acted upon by the multiplication/ division process referred to above, after having its CRC-4 bits extracted and replaced by zeros. The remainder resulting from this division process is then stored and subsequently compared on a bit-bybit basis with the CRC bits received in the next SMF. If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is assumed that the checked SMF is errorfree.
s
s
s
s
s
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms
Several optional algorithms exist in the receive framer. These are selected through programming of register FRM_PR9. CRC-4 Multiframe Alignment Algorithm with 8 ms Timer The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition of assumed frame alignment has been achieved, CRC-4 multiframe alignment is deemed to have occurred if at least two valid CRC-4 multiframe alignment signals can be located within 8 ms, the time separating two CRC-4 multiframe signals being 2 ms or a multiple of 2 ms. The search for the CRC-4 multiframe alignment signal is made only in bit 1 of NOT FAS frames. If multiframe alignment cannot be achieved within 8 ms, it is assumed that frame alignment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initiated. The new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. During this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame alignment (RLFA) state. During the parallel search for basic frame alignment and while in primary basic frame alignment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. The receive framer will continuously search for CRC-4 multiframe alignment.
CRC-4 Multiframe Alignment Algorithm with 100 ms Timer The CRC-4 multiframe alignment with 100 ms timer mode is enabled by setting FRM_PR9 to 0XXXX1X1 (binary). This CRC-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. This is a parallel timer to the 8 ms timer. If CRC-4 multiframe alignment cannot be achieved within the time limit of 100 ms due to the CRC-4 procedure not being implemented at the transmitting side, then an indication is given and actions are taken equivalent to those specified for loss of basic frame alignment, namely:
s
Optional automatic transmission of A = 0 to the line if register FRM_PR27 bit 3 is set to 1. Optional automatic transmission of E = 0 to the line if register FRM_PR28 bit 5 is set to 1. Optional automatic transmission of AIS to the system if register FRM_PR19 bit 1 is set to 1.
s
s
66
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
OUT OF PRIMARY BFA: * OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM * OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE * INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING
NO
PRIMARY BFA SEARCH?
YES IN PRIMARY BFA: * ENABLE TRAFFIC TO THE SYSTEM * TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE * START 8 ms AND 100 ms TIMERS * ENABLE PRIMARY BFA LOSS CHECKING PROCESS YES CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 - NOTE 2) NO PARALLEL BFA SEARCH GOOD?
YES YES CAN CRC-4 MFA BE FOUND IN 8 ms? NO IS INTERNAL 100 ms TRX = 1 ? NO
NO 100 ms TIMER ELAPSED?
YES ASSUME CRC-4 MULTIFRAME ALIGNMENT: * CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA * ADJUST PRIMARY BFA IF NECESSARY SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE: SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1: * OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR THE DURATION OF LTS0MFA = 1 * OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE DURATION OF LTS0MFA = 1 * OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR THE DURATION OF LTSOMFA = 1
YES IS 100 ms TRX = 1 ? NO
SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0: * IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0 * IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABLE DATA TRANSMISSION TO THE SYSTEM INTERFACE * IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1
START CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
YES
CRC-4 COUNT > 914 IN 1 SECOND OR LFA = 1?
NO
CONTINUE CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
5-3909(F).er.2
Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer
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Preliminary Data Sheet October 2000
Frame Formats (continued)
CRC-4 Multiframe Alignment Search Algorithm with 400 ms Timer The CRC-4 multiframe alignment with 400 ms timer mode is enabled by setting FRM_PR9 to 0XXX1XX1 (binary). This receive CRC-4 multiframe reframe mode is the modified CRC-4 multiframe alignment algorithm described in ITU Rec. 706 Annex B, where it is referred to as CRC-4-to-Non-CRC-4 equipment interworking. A flow diagram of this algorithm is illustrated in Figure 27. When the interworking algorithm is enabled, it supersedes the 100 ms algorithm described on page 66 and in Figure 26. This algorithm assumes that a valid basic frame alignment signal is consistently present but the CRC-4 multiframe alignment cannot be achieved by the end of the total CRC-4 multiframe alignment search period of 400 ms, if the distant end is a non-CRC-4 equipment. In this mode, the following consequent actions are taken:
s
s
The loss of basic frame alignment checking process runs continuously, irrespective of the state of the CRC-4 multiframe alignment process below it. A new search for frame alignment is initiated if CRC4 multiframe alignment cannot be achieved in 8 ms, as described in ITU Rec. G.706 Section 4.2. This new search for basic frame alignment will not reset the 400 ms timer or invoke consequent actions associated with loss of the primary basic frame alignment. In particular, all searches for basic frame alignment are carried out in parallel with, and independent of, the primary basic frame loss checking process. All subsequent searches for CRC-4 multiframe alignment are associated with each basic framing sequence found during the parallel search. During the search for CRC-4 multiframe alignment, traffic is allowed through, upon, and to be synchronized to, the initially determined primary basic frame alignment. Upon detection of the CRC-4 multiframe before the 400 ms timer elapsing, the basic frame alignment associated with the CRC-4 multiframe alignment replaces, if necessary, the initially determined basic frame alignment. If CRC-4 multiframe alignment is not found before the 400 ms timer elapses, it is assumed that a condition of interworking between equipment with and without CRC-4 capability exists and the actions described above are taken. If the 2.048 Mbits/s path is reconfigured at any time, then it is assumed that the (new) pair of path terminating equipment will need to re-establish the complete framing process, and the algorithm is reset.
s
s
s
An indication that there is no incoming CRC-4 multiframe alignment signal. All CRC-4 processing on the receive 2.048 Mbits/s signal is inhibited.
s
s
s
CRC-4 data is transmitted to the distant end with both E bits set to zero.
This algorithm allows the identification of failure of CRC-4 multiframe alignment generation/detection, but with correct basic framing, when interworking between each piece of equipment having the modified CRC-4 multiframe alignment algorithm. As described in ITU Rec. G.706 Section B.2.3:
s
s
A 400 ms timer is triggered on the initial recovery of the primary basic frame alignment. The 400 ms timer reset if and only if: -- The criteria for loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 is achieved. -- If 915 out of 1000 errored CRC-4 blocks are detected resulting in a loss of basic frame alignment as described in ITU Rec. G.706 Section 4.3.2. -- On-demand reframe is requested. -- The receive framer is programmed to the non-CRC-4 mode.
s
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
OUT OF PRIMARY BFA: * OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM * OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE * INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING
NO
PRIMARY BFA SEARCH?
YES IN PRIMARY BFA: * ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM * TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE * START 400 ms TIMER * ENABLE PRIMARY BFA LOSS CHECKING PROCESS YES CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2) NO PARALLEL BFA SEARCH ?
NO YES CAN CRC-4 MFA BE FOUND IN 8 ms? NO 400 ms TIMER ELAPSED?
YES ASSUME CRC-4-TO-CRC-4 INTERWORKING: * CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA * ADJUST PRIMARY BFA IF NECESSARY * KEEP A = 0 IN OUTGOING CRC-4 DATA ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING: * CONFIRM PRIMARY BFA * TRANSMIT A BIT = 0 TO THE LINE INTERFACE * TRANSMIT E BIT = 0 TO THE LINE INTERFACE * STOP INCOMING CRC-4 PROCESSING * INDICATE "NO CRC-4 MFA"
START CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
YES
CRC-4 COUNT > 914 IN 1 SECOND OR LFA = 1?
NO
CONTINUE CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
5-3909(F).fr.3
Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Frame Formats (continued)
CEPT Time Slot 16 Multiframe Structure
The T7630 supports two CEPT signaling modes: channel associated signaling (CAS) or per-channel signaling (PCS0 and PCS1). Channel Associated Signaling (CAS) The channel associated signaling (CAS) mode utilizes time slot 16 of the FAS and NOT FAS frames. The CAS format is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pattern of four zeros in bits 1 through 4. Table 33 illustrates the CAS multiframe of time slot 16. The T7630 can be programmed to force the transmitted line CAS multiframe alignment pattern to be transmitted in the FAS frame by selecting the PCS0 option or in the NOT FAS frame by selecting the PCS1 option. Alignment of the transmitted line CAS multiframe to the CRC-4 multiframe is arbitrary. Table 33. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure Time Slot 16 Channel Associated Signaling Multiframe Frame Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 1 0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 2 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 3 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 4 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 5 X0 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 6 YM B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 7 X1 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 8 X2 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30
Notes: Frame 0 bits 1--4 define the time slot 16 multiframe alignment. X0--X2 = time slot 16 spare bits defined in FRM_PR41 bit 0--bit 2. YM = yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Frame Formats (continued)
CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)
Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe alignment state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multiframe 4-bit all-zero patterns is received with an error. Also, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. This state is reported by way of the status registers FRM_SR1 bit 1. Once basic frame alignment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. During a loss of time slot 16 multiframe alignment state:
s s s
CEPT Time Slot 0 FAS/NOT FAS Control Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used to provide added protection against false frame alignment. The sources for the Si bits that are transmitted to the line are the following:
s
CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames. The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0)*.
s
The updating of the signaling data is halted. The received control bits forced to the binary 1 state. The received remote multiframe alarm indication status bit is forced to the binary 0 state. Optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register FRM_PR41 bit 4 is set to 1. Optionally, the transmit framer can transmit the alarm indication signal (AIS) in the system transmit time slot 16 data if register FRM_PR44 bit 6 is set to 1.
s
s
CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm
The time slot 16 multiframe alignment recovery algorithm is as described in ITU Rec. G.732 Section 5.2. The recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preceding time slot 16 contained at least one bit in the binary 1 state.
This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state followed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition (indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations.
s
CEPT with CRC-4: manual transmission of E bit = 0: -- If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit). -- If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is transmitted in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmitted in frame 15.
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment.
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Preliminary Data Sheet October 2000
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
s
NOT FAS Sa-Bit Sources6
The Sa bits, Sa4--Sa8, in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources and value for the Sa bits are:
s
CEPT with CRC-41, automatic transmission of E bit = 0: -- Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section 2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28 bit 3 = 1. -- Optionally, as described in ITU Rec. G.704 Section 2.3.3.4, both E bits are set to 0 while in a received loss of CRC-4 multiframe alignment state2 if FRM_PR28 bit 4 = 1. -- Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multiframe alignment state2 if FRM_PR28 bit 5 = 1.
The Sa source register FRM_PR29 bit 0--bit 4 if FRM_PR29 bit 7--bit 5 = 000 (binary) and FRM_PR30 bit 4--bit 0 = 11111 (binary). The facility data link external input (TFDL) if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 1. The internal FDL-HDLC if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 0. The Sa transmit stack if register FRM_PR29 bit 7--bit 5 are set to 01x (binary). The CHI system interface if register FRM_PR29 bit 7--bit 5 are set to 001 (binary). This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where (1) frames containing Sa bit information have bit 2 of time slot 0 in the binary 1 state and (2) these NOT FAS frames are followed by frames not containing Sa bit information, the FAS frames, which have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Sa received system data to the transmit line Sa data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indicated in the status register, FRM_SR1 bit 4, and then search for the pattern. In the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations.
s
s
s
s
Otherwise, the E bits are transmitted to the line in the 1 state.
NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources
The A bit, as described in ITU Rec. G.704 Section 2.3.2 Table 4a/G.704, is the remote alarm indication bit. In undisturbed conditions, this bit is set to 0 and transmitted to the line. In the loss of frame alignment (LFA) state, this bit may be set to 1 and transmitted to the line as determined by register FRM_PR27. The A bit is set to 1 and transmitted to the line for the following conditions:
s
Setting the transmit A bit = 1 control bit by setting register FRM_PR27 bit 7 to 1. Optionally for the following alarm conditions as selected through programming register FRM_PR27. -- The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 3, or ITU Rec. G.706 Section 4.3.24 if register FRM_PR27 bit 0 = 1. -- The duration of loss of CRC-4 multiframe alignment if register FRM_PR27 bit 2 = 1. -- The duration of loss of signaling time slot 16 multiframe alignment if register FRM_PR27 bit 1 = 1. -- The duration of loss of CRC-4 multiframe alignment after either the 100 ms or 400 ms timer expires if register FRM_PR27 bit 3 = 1. -- The duration of receive Sa6_8hex5 if register FRM_PR27 bit 4 = 1. -- The duration of receive Sa6_Chex5 if register FRM_PR27 bit 5 = 1.
s
1. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment. 2. Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is established, then and only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of LFA and LTS0MFA or in a state of LTS0MFA only, but cannot be in a state of LFA only. 3. LFA is due to framing bit errors. 4. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks. 5. See Table 41 Sa6 Bit Coding Recognized by the Receive Framer, for a definition of this Sa6 pattern. 6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
The receive Sa data is present at:
s s
The Sa received stack, registers FRM_SR54--FRM_SR63, if the T7630 is programmed in the Sa stack mode. The system transmit interface.
The status of the received Sa bits and the received Sa stack is available in status register FRM_SR4. The transmit and receive Sa bit for the FDL can be selected by setting register FRM_PR43 bit 0--bit 2 as shown in Table 166.
Sa Facility Data Link Access
The data link interface may be used to source one of the Sa bits. Access is controlled by registers FRM_PR29, FRM_PR30, and FRM_PR43, see NOT FAS Sa-Bit Sources page 72. The receive Sa data is always present at the receive facility data link output pin, RFDL, along with a valid clock signal at the receive facility clock output pin, RFDLCK. During a loss of frame alignment (LFA) state, the RFDL signal is forced to a 1 state while RFDLCK continues to toggle on the previous frame alignment. When basic frame alignment is found, RFDL is as received from the selected receive Sa bit position and RFDLCK is forced (if necessary) to the new alignment. The data rate for this access mode is 4 kHz. The access timing for the transmit and receive facility data is illustrated in Figure 28 below. During loss of receive clock (LOFRMRLCK), RFDL and RFDLCK are frozen in a state at the point of the LOFRMRLCK being asserted.
t8 TFDLCK t8: TFDLCK CYCLE = 250 s
t9
t9
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
t10: RFDLCK CYCLE = 250 s
RFDLCK
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).dr.1
Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode
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Preliminary Data Sheet October 2000
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
NOT FAS Sa Stack Source and Destination
The transmit Sa4 to Sa8 bits may be sourced from the transmit Sa stack, registers FRM_PR31--FRM_PR40. The Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 34. The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line. The receive stack data, registers FRM_SR54--FRM_SR63, is valid in both the non-CRC-4 mode and the CRC-4 mode. In the non-CRC-4 mode while in the loss of frame alignment (LFA) state, updating of the receive Sa stack is halted and the transmit and receive stack interrupts are deactivated. In the CRC-4 mode while in the loss of time slot 0 multiframe alignment (LTS0MFA) state, updating of the receive Sa stack is halted and the transmit and receive stack interrupts are deactivated. Table 34. Transmit and Receive Sa Stack Structure Register Number 1 2 3 4 5 6 7 8 9 10 Bit 7 (MSB) Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 (LSB) Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
The most significant bit of the first byte is transmitted to the line in frame 1 of a double CRC-4 multiframe. The least significant bit of the second byte is transmitted to the line in frame 31 of the double CRC-4 multiframe. The protocol for accessing the Sa Stack information for the transmit and receive Sa4 to Sa8 bits is shown in Figure 29 and described briefly below. The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 7 (CEPT transmit Sa stack ready) high. At this time, the system has about 4 ms to update the stack. Data written to the stack during this interval will be transmitted during the next double CRC-4 multiframe. By reading register FRM_SR4 bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack is not updated, then the content of the stack is retransmitted to the line. The 32-frame interval of the transmit framer in the non-CRC-4 mode is arbitrary. Enabling transmit CRC-4 mode forces the updating of the internal transmit stack at the end of the 32-frame CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous to the transmit CRC-4 multiframe structure. On the receive side, the T7630 indicates that it has received data in the receive Sa stack, register FRM_SR54-- FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system then has about 4 ms to read the contents of the stack before it is updated again (old data lost). By reading register FRM_SR4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. The receive framer always updates the content of the receive stack so unread data will be overwritten. The last 16 valid Sa4 to Sa8 bits are always stored in the receive Sa stack on a double-multiframe boundary. The 32-frame interval of the receive framer in the non-CRC-4 mode is arbitrary. Enabling the receive CRC-4 mode forces updating of the receive Sa stack at the end of the 32-frame CRC-4 double multiframe. The receive Sa stack is received synchronous to the CRC-4 multiframe structure.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
SYSTEM ACCESS Sa STACK (SASS) INTERVAL: 1) TRANSMIT FRAMER UNIT TRANSMITS TO THE LINE THE DATA IN THE TRANSMIT Sa STACK WRITTEN DURING THE PREVIOUS SASS INTERVAL. 2) THE SYSTEM CAN UPDATE THE TRANSMIT Sa STACK REGISTERS FOR TRANSMISSION IN THE NEXT CRC-4 DOUBLE MULTIFRAME. 3) THE SYSTEM CAN READ THE RECEIVE Sa STACK REGISTERS TO ACCESS THE Sa BITS EXTRACTED DURING THE PREVIOUS VALID (IN MULTIFRAME ALIGNMENT) DOUBLE CRC-4 MULTIFRAME.
START OF CRC-4 DOUBLE MULTIFRAME: * BASIC FRAME ALIGNMENT FOUND, OR, * CRC-4 MULTIFRAME ALIGNMENT FOUND. SYSTEM ACCESS Sa STACK INTERVAL 1-FRAME INTERVAL 1 FRAME 31 FRAMES CRC-4 DOUBLE MULTIFRAME (DMF): 32 FRAMES START FRAME 1 OF 32 IN DMF. 31 FRAMES CRC-4 DOUBLE MULTIFRAME: 32 FRAMES
INTERNAL Sa STACK UPDATE INTERVAL
SYSTEM ACCESS IS DISABLED DURING THIS INTERVAL: 1) THE INTERNAL TRANSMIT Sa STACK IS UPDATED FROM THE FRAMER UNIT'S 10-byte TRANSMIT STACK CONTROL REGISTERS DURING THIS 1-FRAME INTERVAL. 2) ACCESS TO THE STACK CONTROL REGISTERS IS DISABLED DURING THIS 1-FRAME INTERVAL. 3) ONCE LOADED, THE INFORMATION IN THE INTERNAL TRANSMIT Sa STACK IS TRANSMITTED TO THE LINE DURING THE NEXT CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME. 4) IF THE TRANSMIT Sa STACK IS NOT UPDATED, THEN THE CONTENT OF THE TRANSMIT Sa STACKS IS RETRANSMITTED TO THE LINE. 5) THE SYSTEM READ-ONLY RECEIVE STACK IS UPDATED FROM THE INTERNAL RECEIVE STACK INFORMATION REGISTERS. 6) IN NON-CRC-4 MODE, THE RECEIVE Sa STACK EXTRACTING CIRCUITRY ASSUMES AN ARBITRARY DOUBLE 16-FRAME MULTIFRAME STRUCTURE (32 FRAMES), AND DATA IS EXTRACTED ONLY IN THE FRAME ALIGNED STATE. 7) IN CRC-4 MODE, THE RECEIVE Sa STACK INFORMATION IS ALIGNED TO A CRC-4 DOUBLE MULTIFRAME STRUCTURE (32 FRAMES), AND THE DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.
5-3911(F).c
Figure 29. Transmit and Receive Sa Stack Accessing Protocol
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CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
Interrupts indicating the transmit Sa stack or the receive Sa stack are ready for system access are available, see register FRM_SR4 bit 6 and bit 7.
CEPT Time Slot 16 X0--X2 Control Bits
Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0--bit 2. In the loss of TS16 multiframe alignment (LTS16MFA) state, receive X bits are set to 1 in status register FRM_SR53.
The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corresponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling registers, FRM_RSR0-- FRM_RSR23, while receive framer is in both the frame and superframe alignment states. Updating the receive signaling registers can be inhibited on-demand, by setting register FRM_PR44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or superframe alignment state, or a controlled slip event. In the common channel signaling mode, data written in the transmit signaling registers is transmitted in channel 24 of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel 24 is stored in receive signaling registers FRM_RSR0--FRM_RSR23 for T1. Associated Signaling Mode This mode is enabled by setting register FRM_PR44 bit 2 to 1. Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunction with the pay load data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its corresponding 8-bit signaling time slot. The format of the signaling byte is identical to that of the signaling registers. In the ASM mode, writing the transmit signaling registers will corrupt the transmit signaling data. In the transmit signaling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system must write into the F and G bit1 of the transmit signaling registers to program the robbed-bit signaling state mode of each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled.
Signaling Access
Signaling information can be accessed by three different methods: transparently through the CHI, via the control registers, or via the CHI associated signaling mode.
Transparent Signaling
This mode is enabled by setting register FRM_PR44 bit 0 to 1. Data at the received RCHIDATA interface passes through the framer undisturbed. The framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface.
DS1: Robbed-Bit Signaling
Microprocessor Control Registers To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into the F and G bits of the transmit signaling registers, FRM_TSR0-- FRM_TSR23, defines the robbed-bit signaling mode for each channel for both the transmit and receive directions. The per-channel programming allows the system to combine voice channels with data channels within the same frame.
1. All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDATA stream are ignored.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Signaling Access (continued)
Table 35 illustrates the ASM time-slot format for valid channels. Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames DS1: ASM CHI Time Slot 1 2 PAYLOAD DATA 3456 7 8 SIGNALING INFORMATION* A B C D X F G P
* X indicates bits that are undefined by the framer. The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the systeminterface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system interface. Table 36 illustrates the ASM format for T1 stuffed channels used by the T7630. The stuffed data byte contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is ignored. Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels ASM CHI Time Slot 0 1 PAYLOAD DATA 11111 1 SIGNALING INFORMATION* XXXXXXXX
* X indicates bits which are undefined by the framer.
CEPT: Time Slot 16 Signaling
Microprocessor Control Registers To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into transmit signaling control registers FRM_TSR0--FRM_TSR31 define the state of the ABCD bits of time slot 16 transmitted to the line. The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0--FRM_RSR31. Associated Signaling Mode Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit system time slot in conjunction with the data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers. Table 37 illustrates the ASM time-slot format for valid CEPT E1 time slots. Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT CEPT ASM CHI Time Slot 1 2 PAYLOAD DATA 34567 8 SIGNALING INFORMATION A B C D E X* X* P
* In the CEPT formats, these bits are undefined. The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
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Preliminary Data Sheet October 2000
Auxiliary Framer I/O Timing
Transmit and receive clock and data signals are provided by terminals RFRMCK (receive framer clock), RFRMDATA (receive framer data), RFS (receive frame sync), RSSFS (receive framer signaling superframe sync), RCRCMFS (receive frame CRC-4 multiframe sync), TFS (transmit framer frame sync), TSSFS (transmit framer signaling superframe sync), and TCRCMFS (transmit framer CRC-4 multiframe sync). The receive signals are synchronized to the internal recovered receive line clock, RFRMCK, and the transmit signals are synchronized to the transmit line clock, TLCK. Note that TLCK is derived from the external PLLCK which must be phase-locked to the system (CHI) clock, RCHICK, see Table 1, pin 7 and pin 31. Detailed timing specifications for these signals are given in Figure 30--Figure 37.
RFRMCK 125 s RFS
RFRMDATA
BIT 7
BIT 0
BIT 1 TIME SLOT 1
TIME SLOT 24 DATA VALID
5-6290(F)r.5
Figure 30. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode
TLCK 125 s TFS
TPD (SINGLE RAIL) F BIT BIT 0 (MSB)
TS1
TS2
TS24 F BIT BIT 0 (MSB)
TS1
5-6292(F)r.6
Figure 31. Timing Specification for TFS, TLCK, and TPD in DS1 Mode
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Auxiliary Framer I/O Timing (continued)
RFRMCK 125 s RFS
RFRMDATA
BIT 7
BIT 0
BIT 1 FAS/NFAS: TIME SLOT 0
TIME SLOT 31
DATA VALID
5-6294(F)r.5
Figure 32. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode
RFRMCK 125 s RFS 2 ms RSSFS
RFRMDATA TS0 OF THE FRAME AFTER THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000) TS0 OF THE FRAME AFTER THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000)
5-6295(F)r.7
Figure 33. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode
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Preliminary Data Sheet October 2000
Auxiliary Framer I/O Timing (continued)
RFRMCLK
RFS 2 ms RCRCMFS
RFRMDATA TS0 OF FRAME #0 OF MULTIFRAME TS0 OF FRAME #0 OF MULTIFRAME
5-6296(F)r.5
Figure 34. Timing Specification for RCRCMFS in CEPT Mode
TLCK 125 s TFS
TPD (SINGLE RAIL)
TS0 OF FRAME X
TS0 OF FRAME X + 1
5-6297(F)r.5
Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode
TFS 11 CLOCK CYCLES TLCK 2 ms TSSFS
TPD (SINGLE RAIL) TS0 OF THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000)
5-6298(F)r.5
Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode 80 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Auxiliary Framer I/O Timing (continued)
TLCK
TFS 1 ms TCRCMFS 1 ms
TPD (SINGLE RAIL) TS0 OF FRAME #0 OF MULTIFRAME TS0 OF FRAME #8 OF MULTIFRAME TS0 OF FRAME #0 OF MULTIFRAME
5-6299(F)r.5
Figure 37. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode
Alarms and Performance Monitoring
Interrupt Generation
A global interrupt (pin 99) may be generated if enabled by register GREG1. This interrupt is clocked using channel 1 framer receive line clock (RLCK1). If RLCK1 is absent, the interrupt is clocked using RLCK2, the receive line clock of channel 2. If both RLCK1 and RLCK2 are absent, clocking of interrupts is controlled by an interval 2.048 MHz clock generated from the CHI clock. Timing of the interrupt is shown in Figure 38 There is no relation between MPCK (pin 101) and the interrupt, i.e., MPCK maybe asynchronous with any of the other terminator clocks.
RLCK1
INTERRUPT (PIN 99)
5-6563(F)
Figure 38. Relation Between RLCK1 and Interrupt (Pin 99)
Alarm Definition
The receive framer monitors the receive line data for alarm conditions and errored events, and then presents this information to the system through the microprocessor interface status registers. The transmit framer, to a lesser degree, monitors the receive system data and presents the information to the system through the microprocessor interface status registers. Updating of the status registers is controlled by the receive line clock signal. When the receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock the status registers and all status information should be considered corrupted. Lucent Technologies Inc. Lucent Technologies Inc.
Although the precise method of detecting or generating alarm and error signals differs between framing modes, the functions are essentially the same. The alarm conditions monitored on the received line interface are the following: 1. Red alarm or the loss of frame alignment indication (FRM_SR1 bit 0). The red alarm indicates that the receive frame alignment for the line has been lost and the data cannot be properly extracted. The red alarm is indicated by the loss of frame condition for the various framing formats as defined in Table 38. 81
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
Table 38. Red Alarm or Loss of Frame Alignment Conditions Framing Format D4 Number of Errored Framing Bits That Will Cause a Red Alarm (Loss of Frame Alignment) Condition 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. 2 errored FE bits out of 4 consecutive FE bits or, optionally, 320 or more CRC6 errored checksums within a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9. Three consecutive incorrect FAS patterns or three consecutive incorrect NOT FAS patterns; or optionally, greater than 914 received CRC-4 checksum errors in a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.
SLC-96
DDS: Frame ESF
CEPT
2. Yellow alarm or the remote frame alarm (FRM_SR1 bit 0). This alarm is an indication that the line remote end is in a loss of frame alignment state. Indication of remote frame alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in Table 39. Table 39. Remote Frame Alarm Conditions Framing Format Superframe: D4 Superframe: D4-Japanese Superframe: DDS Extended Superframe (ESF) CEPT: Basic Frame CEPT: Signaling Multiframe Remote Frame Alarm Format Bit 2 of all time slots in the 0 state. The twelfth framing bit in the 1 state in two out of three consecutive superframes. Bit 6 of time slot 24 in the 0 state. An alternating pattern of eight ones followed by eight zeros in the ESF data link. Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames. Bit 6 of the time slot 16 signaling frame in the 1 state.
3. Blue alarm or the alarm indication signal (AIS). The alarm indication signal (AIS), sometimes referred to as the blue alarm, is an indication that the remote end is out of service. Detection of an incoming alarm indication signal is defined in Table 40. Table 40. Alarm Indication Signal Conditions Framing Format T1 CEPT ETSI Remote Frame Alarm Format Loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of two consecutive double frame periods (386 bits). As described in ETS 300 233:1994 Section 8.2.2.4, loss of frame alignment occurs and the framer receives a 512 bit period containing two or less binary zeros. This is enabled by setting register FRM_PR10 bit 1 to 0. As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive double frame periods contains three or more zeros or frame alignment signal (FAS) has been found. This is enabled by setting register FRM_PR10 bit 1 to 1.
CEPT ITU
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Alarms and Performance Monitoring (continued)
4. The SLIP condition (FRM_SR3 bit 6 and bit 7). SLIP is defined as the state in which the receive elastic store buffer's write address pointer from the receive framer and the read address pointer from the transmit CHI are equal*.
s
The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (TCHICK) monitoring circuit detects a state of overflow caused by RLCK and TCHICK being out of phase-lock and the period of the received frame being less than that of the system frame. One system frame is deleted. The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (TCHICK) monitoring circuit detects a state of underflow caused by RLCK and TCHICK being out of phase-lock and the period of the received frame being greater than that of the system frame. One system frame is repeated.
s
5. The loss of framer receive clock (LOFRMRLCK, pins 2 and 38). In the framer mode, FRAMER = 0 (pin 41/141), LOFRMRLCK alarm is asserted high when an interval of 250 s has expired with no transition of RLCK (pin 135/47) detected. The alarm is disabled on the first transition of RLCK. In the terminator mode, FRAMER = 1 (pin 41/141), LOFRMRLCK is asserted high when SYSCK (pin 3/35) does not toggle for 250 s. The alarm is disabled on the first transition of SYSCK. 6. The loss of PLL clock (LOPLLCK, pins 39 and 143). LOPLLCK alarm is asserted high when an interval of 250 s has expired with no transition of PLLCK detected. The alarm is disabled 250 s after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 39.
PLLCK 250 s LOPLLCK 250 s
RCHICK
5-6564(F)r.2
Figure 39. Timing for Generation of LOPLLCK (Pin 39/143) 7. Received bipolar violation errors alarm, FRM_SR3 bit 0. This alarm indicates any bipolar decoding error or detection of excessive zeros. 8. Received excessive CRC errors alarm, FRM_SR3 bit 3. In ESF, this alarm is asserted when 320 or more CRC-6 checksum errors are detected within a one second interval. In CEPT, this alarm is asserted when 915 or more CRC-4 checksum errors are detected within a one second interval.
* After a reset, the read and write pointers of the receive path elastic store will be set to a known state.
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Alarms and Performance Monitoring
(continued) 9. The CEPT continuous E-bit alarm (CREBIT) (FRM_SR2 bit 2).
s
11. The 4-bit Sa6 codes (FRM_SR2 bit 3--bit 7). Sa6 codes are asserted if three consecutive 4-bit patterns have been detected. The alarms are disabled when three consecutive 4-bit Sa6 codes have been detected that are different from the pattern previously detected. The receive framer monitors the Sa6 bits for special codes described in ETS Draft prETS 300 233:1992 Section 9.2. The Sa6 codes are defined in Tables 41 and 42. The Sa6 codes in Table 41 may be recognized as an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as the receive framer is in the basic frame alignment state. In the CRC-4 mode, the receive framer can optionally recognize the received Sa6 codes in Table 41 synchronously to the CRC-4 submultiframe structure as long as the receive framer is in the CRC-4 multiframe alignment state (synchronous Sa6 monitoring can be enabled by setting register FRM_PR10 bit 1 to 1). The Sa6 codes in Table 42 are only recognized synchronously to the CRC-4 submultiframe and when the receive framer is in CRC-4 multiframe alignment. The detection of three (3) consecutive 4-bit patterns are required to indicate a valid received Sa6 code. The detection of Sa6 codes is indicated in status register FRM_SR2 bit 3--bit 7. Once set, any three-nibble (12-bit) interval that contains any other Sa6 code will clear the current Sa6 status bit. Interrupts may be generated by the Sa6 codes given in Table 41. Table 41. Sa6 Bit Coding Recognized by the Receive Framer-Asynchronous Bit Stream Code Sa6_8hex Sa6_Ahex Sa6_Chex Sa6_Ehex Sa6_Fhex First Receive Bit (MSB) 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 Last Received Bit (LSB) 0 0 0 0 1
CREBIT is asserted when the receive framer detects: -- Five consecutive seconds where each 1 second interval contains 991 received E bits = 0 events. -- Simultaneously no LFA occurred. -- Optionally, no remote frame alarm (A bit = 1) was detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- Optionally, neither Sa6-Fhex nor Sa6-Ehex codes were detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. -- The five second timer is started when: -- CRC-4 multiframe alignment is achieved. -- And optionally, A = 0 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- And optionally, neither Sa6_Fhex1 nor Sa6_Ehex* is detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. The five second counter is restarted when: -- LFA occurs, or -- 990 E bit = 0 events occur in 1 second, or -- Optionally, an A bit = 1 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- Optionally, a valid Sa6 pattern 1111 (binary) or Sa6 pattern 1110 (binary) code was detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1.
s
This alarm is disabled during loss of frame alignment (LFA) or loss of CRC-4 multiframe alignment (LTS0MFA). 10. Failed state alarm or the unavailable state alarm, FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit 7. This alarm is defined as the unavailable state at the onset of ten consecutive severely errored seconds. In this state, the receive framer inhibits incrementing of the severely errored and errored second counters for the duration of the unavailable state. The receive framer deasserts the unavailable state condition at the onset of ten consecutive errored seconds which were not severely errored.
* See Table 41, Sa6 Bit Coding Recognized by the Receive Framer, for a definition of this Sa6 pattern.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Alarms and Performance Monitoring (continued)
Table 42 defines the three 4-bit Sa6 codes that are always detected synchronously to the CRC-4 submultiframe structure and are only used for counting NT1 events. Table 42. Sa6 Bit Coding Recognized by the Receive Frame-Synchronous Bit Stream Code Sa6_1hex Sa6_2hex Sa6_3hex First Receive Bit (MSB) 0 0 0 0 0 0 0 1 1 Last Received Bit (LSB) 1 0 1 Event at NT1 E=0 CRC-4 Error CRC-4 Error & E = 0 This code will cause both counters to increment. Counter Size (bits) 16 16 --
The reference points for receive CRC-4, E bit, and Sa6 decoding are illustrated in Figure 40.
T REFERENCE POINT NT2 (NT1 REMOTE) NT1
V REFERENCE POINT ET
CRC ERROR DETECTED
CRC ERROR DETECTED
E BIT = 0
CRC-4 ERRORS AT THE ET, E BIT = 0, ERROR EVENT AT THE ET REMOTE
E BIT = 0
Sa6 CRC-4 ERRORS DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 001X E = 0 DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 00X1 CRC-4 ERRORS AT THE NT1 E BIT = 0, ERROR EVENT DETECTED AT THE NT1 REMOTE COUNT: 1) CRC ERRORS, 2) E = 0, 3) Sa6 = 001X, AND 4) Sa6 = 00X1
5-3913(F)r.8
Figure 40. The T and V Reference Points for a Typical CEPT E1 Application 12. CEPT auxiliary pattern alarm (AUXP) (FRM_SR1 bit 6). The received auxiliary alarm, register FRM_SR1 bit 6 (AUXP), is asserted when the receive framer is in the LFA state and has detected more than 253 10 (binary) patterns for 512 consecutive bits. In a 512-bit interval, only two 10 (binary) patterns are allowable for the alarm to be asserted and maintained. The 512-bit interval is a sliding window determined by the first 10 (binary) pattern detected. This alarm is disabled when three or more 10 (binary) patterns are detected in 512 consecutive bits. The search for AUXP is synchronized with the first alternating 10 (binary) pattern as shown in Table 43. Table 43. AUXP Synchronization and Clear Sychronization Process 00 -- 10 sync 10 -- 01 -- 11 -- 11 clear sync 00 -- 00 -- 0 -- 10 sync 00 ... 10 ...
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Alarms and Performance Monitoring (continued)
Event Counters Definition
The error events monitored in the receive framer's status registers are defined in Table 44 for the hardwired (default) threshold values. The errored second and severely errored second threshold registers can be programmed through FRM_PR11--FRM_PR13 such that the errored and severely errored second counters function as required by system needs. DS1 errors are reported in the ET error registers, FRM_SR20 through FRM_SR35. For the framer to correctly report coding and BPV errors, the LIU/framer interface must ber configured as dual-rail mode. Table 44. Event Counters Definition Error Event Bipolar Violations (BPVs) Functional Mode AMI B8ZS Definition Counter Size (bits) 16
Frame Alignment Errors (FERs)
CRC Checksum Errors Excessive CRC Errors Received E bits = 0 Errored Second Events
Any bipolar violation or 16 or more consecutive zeros. Any BPV, code violation, or any 8-bit interval with no one pulse. CEPT HDB3 Any BPV, code violation, or any 4-bit interval with no one pulse. SF: D4 Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any FT bit errors (FRM_PR10 bit 2 = 0). Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any FT SF: SLC-96 bit errors (FRM_PR10 bit 2 = 0). SF: DDS Any FT, FS, or time slot 24 FAS bit error. ESF Any FE bit error. CEPT Any FAS (0011011) or NOT FAS (bit 2) bit error. ESF or CEPT with Any received checksum in error. CRC 320 checksum errors in a one second interval. ESF CEPT with CRC 915 checksum errors in a one second interval. CEPT with CRC-4 E bits = 0 in frame 13 and frame 15. All Any one of the relevant error conditions enabled in registers FRM_PR14--FRM_PR18 within a one second interval. Any framing bit errors within a one second interval. Any CRC-6 errors within a one second interval. Any framing errors within a one second interval. Any CRC-4 errors within a one second interval. Any E bit = 0 event within a one second interval. Any Sa6 = 001x (binary) code event within a one second interval. Any Sa6 = 00x1 (binary) code event within a one second interval.
16
16 NONE 16 16
DS1: non ESF DS1: ESF CEPT without CRC-4 CEPT with CRC-4 (ET1) CEPT with CRC-4 (ET1 remote) CEPT with CRC-4 (NT1) CEPT with CRC-4 (NT1 remote)
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Alarms and Performance Monitoring (continued)
Table 44. Event Counters Definition (continued) Error Event Bursty Errored Second Events Functional Mode DS1: non ESF DS1: ESF CEPT without CRC-4 CEPT with CRC-4 (ET1) CEPT with CRC-4 (ET1 remote) CEPT with CRC-4 (NT1) CEPT with CRC-4 (NT1 remote) All Definition Greater than 1 but less than 8 framing bit errors within a one second interval. Greater than 1 but less than 320 CRC-6 errors within a one second interval. Greater than 1 but less than 16 framing bit errors within a one second interval. Greater than 1 but less than 915 CRC-4 errors within a one second interval. Greater than 1 but less than 915 E bit = 0 events within a one second interval. Greater than 1 but less than 915 Sa6 = 001x (binary) code events within a one second interval. Greater than 1 but less than 915 Sa6 = 00x1 (binary) code events within a one second interval. Any one of the relevant error conditions enabled in registers FRM_PR14--FRM_PR18 within a one second interval. 8 or more framing bit errors within a one second interval. 320 or more CRC-6 errors within a one second interval. 16 or more framing bit errors within a one second interval. 915 or more CRC-4 errors within a one second interval. 915 or more E bit = 0 events within a one second interval. 915 or more Sa6 = 001x (binary) code events within a one second interval. 915 or more Sa6 = 00x1 (binary) code events within a one second interval. A one second period in the unavailable state. Counter Size (bits) 16
Severely Errored Second Events
16
DS1: non ESF DS1: ESF CEPT with no CRC-4 CEPT with CRC-4 (ET1) CEPT with CRC-4 (ET1 remote) CEPT with CRC-4 (NT1) CEPT with CRC-4 (NT1 remote) All
Unavailable Second Events
16
The receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second events. When in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten consecutive seconds which were not severely errored.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Alarms and Performance Monitoring
(continued)
s
Loopback and Transmission Modes
Primary Loopback Modes Framer primary loopback mode is controlled by register FRM_PR24. There are seven primary loopback and transmission test modes supported:
s s s s s s s
Line loopback (LLB). Board loopback (BLB). Single time-slot system loopback (STSSLB). Single time-slot line loopback (STSLLB). CEPT nailed-up broadcast transmission (CNUBT). Payload loopback (PLLB). CEPT nailed-up connect loopback (CNUCLB).
s s
The STSLLB mode loops one and only one received line time slot back to the transmit line. The selected time-slot data is looped to the line after being processed by the receive framer, and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen). This mode can be selected by setting register FRM_PR24 to 100A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. The CNUBT mode transmits received-line time slot X to the system in time slots X and time slot 0 (of the next frame). Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to 101A4A3A2A1A0 where A4A3A2A1A0 is the binary address of the selected time slot. The PLLB mode loops the received line data and clock back to the transmit line while inserting (replacing) the facility data link in the looped back data. Two variations of the payload loopback are available. In the pass through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and CRC bits are looped back to the line transmit data. In the regenerated framing/CRC bit mode (chosen by setting register FRM_PR24 to 110xxxxx (binary) and register FRM_PR10 bit 3 to 0), the framing and CRC bits are regenerated by the transmit framer. The payload loopback is only available for ESF and CEPT modes. The CNUCLB mode loops received system time slot X back to the system in time slot 0. The selected time slot is not routed through the receive elastic store buffer and therefore will not be affected by systemAIS, RLFA conditions, or controlled slips. Any time slot can be looped back to the system. Time slot X transmitted to the line is not affected by this loopback mode. Looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the FAS and NOT FAS data in time slot 0 transmitted to the line. This mode can be selected by setting register FRM_PR24 to 110A4A3A2A1A0 and register FRM_PR10 bit 3 to 1, where A4A3A2A1A0 is the binary address of the selected time slot.
The loopback and transmission modes are described in detail below:
s
The LLB mode loops the receive line data and clock back to the transmit line. The received data is processed by the receive framer and transmitted to the system interface. This mode can be selected by setting register FRM_PR24 to 001xxxxx (binary). The BLB mode loops the receive system data back to the system after: -- The transmit framer processes the data, and -- The receive framer processes the data. -- In the BLB mode, AIS is always transmitted to the line interface. This mode can be selected by setting register FRM_PR24 to 010xxxxx (binary). The STSSLB mode loops one and only one received system time slot back to the transmit system interface. The selected looped back time-slot data is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Once selected, the desired time-slot position has the programmable idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. This mode can be selected by setting register FRM_PR24 to 011A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot.
s
s
s
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
loopback mode will control that time slot. Once selected, the desired time-slot position has the programmable line idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback.
s
Alarms and Performance Monitoring
(continued) Secondary Loopback Modes There are two secondary loopback modes supported:
s
Secondary-single time-slot system loopback (S-STSSLB) Secondary-single time-slot line loopback (S-STSLLB) The secondary-STSSLB mode loops one and only one received system time slot back to the transmit system interface. The selected time-slot data looped back is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Whenever the secondary loopback register is programmed to the same time slot as the primary register, the primary
s
The loopbacks are described in detail below:
s
The secondary-STSLLB mode loops one and only one line time slot back to the line. The selected time slot data is looped to the line after being processed by the receive framer and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen in this mode).
Table 45 defines the deactivation of the two secondary loopback modes as a function of the activation of the primary loopback and test transmission modes.
Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the Primary Loopback Modes Primary Loopback Mode STSSLB STSLLB BLB CNUBT LLB NUCLB PLLB Deactivation of S-STSSLB If primary time slot = secondary If primary time slot = secondary Always If the secondary time slot is TS0 or if the primary time slot = secondary Always If the secondary time slot is TS0 or if the primary time slot = secondary Always Deactivation of S-STSLLB If primary time slot = secondary If primary time slot = secondary Always If primary time slot = secondary Always If primary time slot = secondary Always
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
Figure 41 illustrates the various loopback modes implemented by each framer unit.
FRAMER SYSTEM ES
RECEIVE SYSTEM DATA IS IGNORED LINE SYSTEM
AIS LINE
(1) LINE LOOPBACK TRANSMIT PROGRAMMABLE LINE IDLE CODE IN REGISTER FRM_PR22 IN OUTGOING LINE TS-X FRAMER LINE ES SYSTEM LOOPBACK TS-X LINE
(2) BOARD LOOPBACK TRANSMIT PROGRAMMABLE IDLE CODE IN REGISTER FRM_PR22 IN OUTGOING SYSTEM TS-X INSERT ONLY TIME SLOT X SYSTEM ES
(3) SINGLE TIME-SLOT SYSTEM LOOPBACK
(4) SINGLE TIME-SLOT LINE LOOPBACK
FRAMER LINE ES SYSTEM LINE
TRANSMIT FRAMER
SYSTEM
TRANSMIT LINE TS-X IN SYSTEM TS-X AND SYSTEM TS-0 (5) CEPT NAILED-UP BROADCAST TRANSMISSION FRAMER LINE ES LOOPBACK TS-X IN TS-0
(6) PAYLOAD LINE LOOPBACK
SYSTEM
(7) CEPT NAILED-UP CONNECT LOOPBACK
5-3914(F).cr.3
Figure 41. Loopback and Test Transmission Modes
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Alarms and Performance Monitoring (continued)
Line Test Patterns
Test patterns may be transmitted to the line through either register FRM_PR20 or register FRM_PR69. Only one of these sources may be active at the same time. Signaling must be inhibited while sending these test patterns. Transmit Line Test Patterns--Using Register FRM_PR20 The transmit framer can be programmed through register FRM_PR20 to transmit various test patterns. These test patterns, when enabled, overwrite the received CHI data. The test patterns available using register FRM_PR20 are:
s
The unframed-AIS pattern which consists of a continuous bit stream of ones (. . . 111111 . . .) enabled by setting register FRM_PR20 bit 0 to 1. The unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and zeros (. . . 10101010 . . .) enabled by setting register FRM_PR20 bit 1 to 1. The quasi-random test signal, enabled by setting register FRM_PR20 bit 3 to 1, which consists of: -- A pattern produced by means of a twenty-stage shift register with feedback taken from the 17th and 20th stages via an exclusive-OR gate to the first stage. The output is taken from the 20th stage and is forced to a 1 state whenever the next 14 stages (19 through 6) are all 0. The pattern length is 1,048,575 or 220 - 1 bits. This pattern is described in detail in AT&T Technical Reference 62411 [5] Appendix and illustrated in Figure 42. -- Valid framing bits. -- Valid transmit facility data link (TFDL) bit information. -- Valid CRC bits.
s
s
A B
C XOR
D #1
D #2 D-TYPE FLIP-FLOPS
D #17
D #18
D #19
D #20
#6 #19 NOR #20
QUASI-RANDOM TEST OUTPUT
OR
5-3915(F).dr.1
Figure 42. 20-Stage Shift Register Used to Generate the Quasi-Random Signal The pseudorandom test pattern, enabled by setting register FRM_PR20 bit 2 to 1, which consists of: -- A 215- 1 pattern inserted in the entire payload (time slots 1--24 in DS1 and time slots 1--32 in CEPT), as described by ITU Rec. 0.151 and illustrated in Figure 43. -- Valid framing pattern. -- Valid transmit facility data link (TFDL) bit data. -- Valid CRC bits. 91
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
A B
C
D #1
D #2
D #3
D #13
D #14
D PSEUDORANDOM #15 TEST OUTPUT
XOR
D-TYPE FLIP-FLOPS
5-3915(F).er.1
Figure 43. 15-Stage Shift Register Used to Generate the Pseudorandom Signal The idle code test pattern, enabled by setting register FRM_PR20 bit 6 to 1, which consists of: -- The programmable idle code, programmed through register FRM_PR22, in time slots 1--24 in DS1 and 0--31 in CEPT. -- Valid framing pattern. -- Valid transmit facility data link (TFDL) bit data. -- Valid CRC bits.
s
Transmit Line Test Patterns--Using Register FRM_PR69 Framed or unframed patterns indicated in Table 46 may be generated and sent to the line by register FRM_PR69 and by setting register FRM_PR20 to 00 (hex). Selection of transmission of either a framed or unframed test pattern is made through FRM_PR69 bit 3. If one of the test patterns of register FRM_PR69 is enabled, a single bit error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1. Table 46. Register FRM_PR69 Test Patterns Register FRM_PR69 Bit 7 Bit 6 Bit 5 Bit 4 MARK (all ones AIS) 0 0 0 0 20 0 0 0 1 QRSS (2 - 1 with zero suppression) 0 0 1 0 25 - 1 63 (26 - 1) 511 (29 - 1) 511 (29 - 1) reversed 2047 (211 - 1) 2047 (211 - 1) reversed 215 - 1 220 - 1 220 - 1 223 - 1 1:1 (alternating) 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 Pattern
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
To establish lock to the pattern, 256 sequential bits must be received without error. When lock to the pattern is achieved, the appropriate bit of register FRM_SR7 is set to a 1. Once pattern lock is established, the monitor can withstand up to 32 single bit errors per frame without a loss of lock. Lock will be lost if more than 32 errors occur within a single frame. When such a condition occurs, the appropriate bit of register FRM_SR7 is deasserted. The monitor then resumes scanning for pattern candidates. Receive Line Pattern Detector--Using Register FRM_PR70 Framed or unframed patterns indicated in Table 47 may be detected using register FRM_PR70. Detection of the selected test pattern is indicated when register FRM_SR7 bit 4 is set to 1. Selection of a framed or unframed test pattern is made through FRM_PR70 bit 3. Bit errors in the received test pattern are indicated when register FRM_SR7 bit 5 = 1. The bit errors are counted and reported in registers FRM_SR8 and FRM_SR9, which are normally the BPV counter registers. (In this test mode, the BPV counter registers do not count BPVs but count only bit errors in the received test pattern.)
Alarms and Performance Monitoring
(continued) Receive Line Pattern Monitor--Using Register FRM_SR7 The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed patterns, and indicates detection in register FRM_SR7 bit 6 and bit 7.
s
The pseudorandom test pattern as described by ITU Rec. O.151 and illustrated in Figure 43. Detection of the pattern is indicated by register FRM_SR7 bit 6 = 1. The quasi-random test pattern described in AT&T Technical Reference 62411[5] Appendix and illustrated in Figure 42. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1.
s
In DS1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. In CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information. No signaling, robbed bit in the case of T1 and TS16 signaling in the case of CEPT, may be present for successful detection of these two test patterns. Table 47. Register FRM_PR70 Test Patterns Pattern
Register FRM_PR70 Bit 7 Bit 6 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0
MARK (all ones AIS) QRSS (220 - 1 with zero suppression) 25 - 1 63 (26 - 1) 511 (29 - 1) 511 (29 - 1) reversed 2047 (211 - 1) 2047 (211 - 1) reversed 215 - 1 220 2
20
0 0 0 0 0 0 0 0 1 1 1 1 1
-1 -1
223 - 1 1:1 (alternating)
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
The pattern detector continuously monitors the received line for the particular pattern selected in register FRM_PR70 bit 7--bit 4 (DPTRN). To establish detector lock to the pattern, 256 sequential bits must be detected. Once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register FRM_PR70 bit 2 (DBLKSEL) is set to 0. To select a pattern or change the pattern to be detected, the following programming sequence must be followed.
s s s
DBLKSEL (register FRM_PR70 bit 2) is set to 0. The new pattern to be detected is selected by setting register FRM_PR70 bit 7--bit 4 to the desired value. DBLKSEL (register FRM_PR70 bit 2) is set to 1.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Alarms and Performance Monitoring (continued)
Automatic and On-Demand Commands
Various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. After reset, all automatic transmissions are disabled. The user can enable the automatic or on-demand actions by setting the proper bits in the automatic and on-demand action registers as identified below in Table 48. Table 48 shows the programmable automatically transmitted signals and the triggering mechanisms for each. Table 49 shows the on-demand commands. Table 48. Automatic Enable Commands Action Transmit Remote Frame Alarm (RFA) Trigger Loss of frame alignment (RLFA). Loss of CEPT time slot 16 multiframe alignment (RTS16LMFA). Loss of CEPT time slot 0 multiframe alignment (RTS0LMFA). Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment. Detection of the CEPT RSa6 = 8 (hex) code. Detection of the CEPT RSa6 = C (hex) code. Detection of CEPT CRC-4 error. RTS0LMFA. Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment. RLFA. Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment. RTS16LMFA. Enabling Register Bit FRM_PR27 bit 0 = 1 FRM_PR27 bit 1 = 1 FRM_PR27 bit 2 = 1 FRM_PR27 bit 3 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR27 bit 4 = 1 FRM_PR27 bit 5 = 1 FRM_PR28 bit 3 = 1 FRM_PR28 bit 4 = 1 FRM_PR28 bit 5 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR19 bit 0 = 1 FRM_PR19 bit 1 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR41 bit 4 = 1
Transmit CEPT E Bit = 0
Transmit AIS to System
Transmit CEPT Time Slot 16 Remote Multiframe Alarm to Line Transmit CEPT AIS in Time Slot 16 to System Automatic Enabling of DS1 Line Loopback On/Off Automatic Enabling of ESF FDL Line Loopback On/Off Automatic Enabling of ESF FDL Payload Loopback On/Off
RTS16LMFA. Line loopback on/off code. ESF line loopback on/off code. ESF payload loopback on/off code.
FRM_PR44 bit 6 = 1 FRM_PR19 bit 4 =1 FRM_PR19 bit 6 =1 FRM_PR19 bit 7 =1
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
Table 49. On-Demand Commands Type Frame Format D4 (US) DDS ESF CEPT Transmit Time Slot 16 Remote Multiframe Alarm to the Line Transmit Data Link AIS (Squelch) Transmit Line Test Patterns CEPT Action Bit 2 of all time slots = 0. Bit 6 in time slot 24 = 0. Pattern of 1111111100000000 in the FDL F-bit position. A bit = 1. Time slot 16 remote alarm bit = 1. Transmit data link bit = 1. Transmit test patterns to the line interface. FRM_PR41 bit 5 = 1 FRM_PR21 bit 4 = 1 See Line Test Patterns section on page 91 and Transmit Line Test Patterns--Using Register FRM_PR69 section on page 92. FRM_PR19 bit 3 = 1 FRM_PR44 bit 1 = 1 FRM_PR44 bit 7 = 1 FRM_PR44 bit 3 = 1 FRM_PR26 bit 2 = 1 FRM_PR41 bit 6 = 1 See Loopback and Transmission Modes section on page 88. Enabling Register Bit FRM_PR27 bit 6 = 1 FRM_PR27 bit 7 = 1
Transmit Remote Frame Alarm D4 (Japanese) FS bit in frame 12 = 1.
SLC-96, ESF
All
Transmit System AIS Transmit System Signaling AIS (Squelch)
All T1 CEPT
Transmits AIS to the system. Transmit ABCD = 1111 to the system. Transmit AIS in system time slot 16. Suspend the updating of the receive signaling registers. Force the receive framer to reframe. Transmit AIS in time slot 16 to the line. Enables system and line loopbacks.
Receive Signaling Inhibit Receive Framer Reframe Transmit Line Time Slot 16 Enable Loopback
All All CEPT All
Framer Software Reset
All
The framer and FDL are placed in FRM_PR26 bit 0 = 1 the reset state for four RCLK clock cycles. The framer parameter registers are forced to the default value. The framer and FDL are placed in FRM_PR26 bit 1 = 1 the reset state as long as this bit is set to 1. The framer parameter registers are not changed from their programmed values.
Framer Software Restart
All
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL)
Data may be extracted from and inserted into the facility data link in SLC-96, DDS, ESF, and CEPT framing formats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register FRM_PR43 bit 0--bit 2. Access to the FDL is made through:
s s
The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 28 shows the timing of these signals. The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC section may beframed in HDLC format or passed through transparently
t8 TFDLCK t8: TFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES) t9 t9
.
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
RFDLCK
t10: RFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES)
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).cr.1
Figure 44. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections In the ESF frame format, automatic assembly and transmission of the performance report message (PRM) as defined in both ANSI T1.403-1995 and Bellcore's TR-TSY-000194 Issue 1, 12--87 is managed by the receive framer and transmit FDL sections. The ANSI T1.403-1995 bit-oriented data link messages (BOM) can be transmitted by the transmit FDL section and recognized and stored by the receive FDL section.
Receive Facility Data Link Interface
Summary A brief summary of the receive facility data link functions is given below:
s
Bit-oriented message (BOM) operation. The ANSI T1.403-1995 bit-oriented data link messages are recognized and stored in register FDL_SR3. The number of times that an ANSI code must be received for detection can be programmed from 1 to 10 by writing to register FDL_PR0 bit 4-- bit 7. When a valid ANSI code is detected, register FDL_SR0 bit 7 (FRANSI) is set. HDLC operation. This is the default mode of operation when the FDL receiver is enabled (register FDL_PR1 bit 2 = 1). The HDLC framer detects the HDLC flags, checks the CRC bytes, and stores the data in the FDL receiver FIFO (register FDL_SR4) along with a status of frame (SF) byte. HDLC operation with performance report messages (PRM). This mode is enabled by setting register FDL_PR1 bit 2 and bit 6 to 1. In this case, the receive FDL will store the 13 bytes of the PRM report field in the FDL receive FIFO (register FDL_SR4) along with a status of frame (SF) byte. 97
s
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Facility Data Link (FDL) (continued)
s
Transparent operation. Enabling the FDL and setting register FDL_PR9 bit 6 (FTM) to 1 disables the HDLC processing. Incoming data link bits are stored in the FDL receive FIFO (register FDL_SR4). Transparent operation with pattern match. Enabling the FDL and setting registers FDL_PR9 bit 5 (FMATCH) and FDL_PR9 bit 6 (FTM) to 1 forces the FDL to start storing data in the FDL receive FIFO (register FDL_SR4) only after the programmable match character defined in register FDL_PR8 bit 0--bit 7 has been detected. The match character and all subsequent bytes are placed into the FDL receive FIFO.
s
The FDL interface to the receive framer is illustrated in Figure 45.
RECEIVE LINE DATA
LOSS OF FRAME ALIGNMENT RECEIVE FRAMER
RECEIVE FDL DATA EXTRACTER RFDL RFDLCK RFDL RECEIVE FACILITY DATA RECEIVE FACILITY DATA LINK HDLC
TRANSPARENT RFDLCK
ANSI T1.403-1995 BIT-ORIENTED DATA LINK MESSAGES MONITOR
ONE 8-bit REGISTER IDENTIFYING THE ESF BIT-ORIENTED CODE
RECEIVE FACILITY DATA LINK FIFO 64 8-bit LOCATIONS
MICROPROCESSOR INTERFACE
5-4560(F).a
Figure 45. Block Diagram for the Receive Facility Data Link Interface Receive ANSI T1.403 Bit-Oriented Messages (BOM)
s
The receive FDL monitor will detect any of the ANSI T1.403 ESF bit-oriented messages (BOMs) and generate an interrupt, enabled by register FDL_PR6 bit 7, upon detection. Register FDL_SR0 bit 7 (FRANSI) is set to 1 upon detection of a valid BOM and then cleared when read. The received ESF FDL bit-oriented messages are received in the form 111111110X0X1X2X3X4X50 (the left-most bit is received first). The bits designated as X are the defined ANSI ESF FDL code bits. These code bits are written into the received ANSI FDL status register FDL_SR3 when the entire code is received. The minimum number of times a valid code must be received before it is reported can be programmed from 1 to 10 using register FDL_PR0 bit 4--bit 7.
s
s
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL) (continued)
The received ANSI FDL status byte, register FDL_SR3, has the following format. Table 50. Receive ANSI Code B7 0 B6 0 B5 X5 B4 X4 B3 X3 B2 X2 B1 X1 B0 X0
Receive ANSI Performance Report Messages (PRM) As defined in ANSI T1.403, the performance report messages consist of 15 bytes, starting and ending with an HDLC flag. The receive framer status information consists of four pairs of octets, as shown in Table 51. Upon detection of the PRM message, the receive FDL extracts the 13 bytes of the PRM report field and stores it in the receive FDL FIFO along with the status of frame byte. Table 51. Performance Report Message Structure* Octet PRM B7 PRM B6 PRM B5 PRM B4 PRM B3 PRM B2 PRM B1 PRM B0 Number 1 2 3 4 5 6 7 8 9 10 11 12 13--14 15 Flag SAPI TEI Control U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R FCS Flag C/R EA EA G6 Nl G6 Nl G6 Nl G6 Nl
G3 FE G3 FE G3 FE G3 FE
LV SE LV SE LV SE LV SE
G4 LB G4 LB G4 LB G4 LB
G5 G2 G5 G2 G5 G2 G5 G2
SL Nm SL Nm SL Nm SL Nm
* The rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the FCS that are transmitted leftmost bit (bit 8) first.
The definition of each PRM field is shown in Table 52, and octet content is shown in Table 53.
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Preliminary Data Sheet October 2000
Facility Data Link (FDL) (continued)
Table 52. FDL Performance Report Message Field Definition PRM Field G1 = 1 G2 = 1 G3 = 1 G4 = 1 G5 = 1 G6 = 1 SE = 1 FE =1 LV = 1 SL = 1 LB = 1 U1, U2 = 0 R=0 Nm, Nl = 00, 01, 10, 11 Definition CRC Error Event = 1 1 < CRC Error Event 5 5 < CRC Error Event 10 10 < CRC Error Event 100 100 < CRC Error Event 319 CRC Error Event 320 Severely Errored Framing Event 1 (FE will = 0) Frame Synchronization Bit Error Event 1 (SE will = 0) Line Code Violation Event 1 Slip Event 1 Payload Loopback Activated Reserved Reserved (default value = 0) One-Second Report Modulo 4 Counter
Table 53. Octet Contents and Definition Octet Number 1 2 3 4 5, 6 7, 8 9, 10 11, 12 13, 14 15 Octet Contents 01111110 00111000 00111010 00000001 00000011 Variable Variable Variable Variable Variable 01111110 Definition Opening LAPD Flag From CI: SAPI = 14, C/R = 0, EA = 0 From Carrier: SAPI = 14, C/R = 1, EA = 0 TEI = 0, EA = 1 Unacknowledged Frame Data for Latest Second (T) Data for Previous Second (T - 1) Data for Earlier Second (T - 2) Data for Earlier Second (T - 3) CRC-16 Frame Check Sequence Closing LAPD Flag
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Facility Data Link (FDL) (continued)
Receive HDLC Mode This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received HDLC frame are not stored in the receive FIFO. When receiving ANSI PRM frames, the frame check sequence bytes are stored in the receive FIFO. The SF byte has the following format. Table 54. Receive Status of Frame Byte
RSF B7 BAD CRC RSF B6 ABORT RSF B5 RFIFO OVERRUN RSF B4 BAD BYTE COUNT RSF B3 0 RSF B2 0 RSF B1 0 RSF B0 0
Bit 7 of the SF status byte is the CRC status bit. A 1 indicates that an incorrect CRC was detected. A 0 indicates the CRC is correct. Bit 6 of the SF status byte is the abort status. A 1 indicates the frame associated with this status byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing flag). An abort can also cause bits 7 and/or 4 to be set to 1. An abort is not reported when a flag is followed by seven ones. Bit 5 is the FIFO overrun bit. A 1 indicates that a receive FIFO overrun occurred (the 64-byte FIFO size was exceeded). Bit 4 is the FIFO bad byte count that indicates whether or not the bit count received was a multiple of eight (i.e., an integer number of bytes). A 1 indicates that the bit count received after 0-bit deletion was not a multiple of eight, and a 0 indicates that the bit count was a multiple of eight. When a nonbyte-aligned frame is received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than eight valid data bits. The HDLC block provides no indication of how many of the bits in the byte are valid. User application programming controls processing of nonbyte-aligned frames. Bit 3--bit 0 of the SF status byte are not used and are set to 0. A good frame is implied when the SF status byte is 00 (hex).
Receive FDL FIFO Whenever an SF byte is present in the receive FIFO, the end of frame registers FDL_SR0 bit 4 (FREOF) and FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue status (register FDL_SR2 bit 0--bit 6) bits report the number of bytes up to and including the first SF byte. If no SF byte is present in the receive FIFO, the count directly reflects the number of data bytes available to be read. Depending on the FDL frame size, it is possible for multiple frames to be present in the receive FIFO. The receive fill level indicator register FDL_PR6 bit 0--bit 5 (FRIL) can be programmed to tailor the service time interval to the system. The receive FIFO full register FDL_SR0 bit 3 (FRF) interrupt is set in the interrupt status register when the receive FIFO reaches the preprogrammed full position. An FREOF interrupt is also issued when the receiver has identified the end of frame and has written the SF byte for that frame. An FDL overrun interrupt register FDL_SR0 bit 5 (FROVERUN) is generated when the receiver needs to write either status or data to the receive FIFO while the receive FIFO is full. An overrun condition will cause the last byte of the receive FIFO to be overwritten with an SF byte indicating the overrun status. A receive idle register FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous ones have been detected.
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Facility Data Link (FDL) (continued)
The receive queue status bits, register FDL_SR2 bit 0--bit 6 (FRQS), are updated as bytes are loaded into the receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO, register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0--bit 6 = 0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the queue status decrements with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0 when the FIFO is completely empty. Thus, the FRQS and FREOF bits provide a mechanism to recognize the end of 1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be present in the FIFO. The FRQS reports only the number of bytes to the first SF status byte. If FRQS is 0, do not read the receive FIFO. A read will result in corruption of receive FIFO. To allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in register FDL_PR6 bit 0--bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits and FREOF bit allow the user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an FRF interrupt.
Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the FRF interrupt be masked FRFIE = 0 and the interrupt register be read at the end of the service routine, discarding any FRF interrupt seen before unmasking the FRF interrupt. Receiver Overrun A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data or SF status) being overwritten. The overrun condition is reported in register FDL_SR0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5 and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF status byte.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL) (continued)
Transmit Facility Data Link Interface
The FDL interface of the transmit framer is shown in Figure 46, indicating the priority of the FDL sources. The remote frame alarm, enabled using register FRM_PR27, is given the highest transmission priority by the transmit framer. The ANSI T1.403-1995 bit-oriented data link message transmission is given priority over performance report messages, and the automatic transmission of the performance report messages is given priority over FDL HDLC transmission. Idle code is generated by the FDL unit when no other transmission is enabled. The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1.
MICROPROCESSOR INTERFACE
TRANSMIT FDL FIFO TRANSPARENT
RECEIVE FRAMER
TRANSMIT FDL HDLC FRAMER
TRANSMIT PERFORMANCE REPORT MESSAGE ASSEMBLER
TFDL
TRANSMIT ANSI T1.403 FDL BIT CODE GENERATOR
FDL IDLE CODE GENERATOR FDL YELLOW ALARM
TFDLCK
TRANSMIT FDL CLOCK GENERATOR
TFDLCK
TRANSMIT FRAME ASSEMBLER
5-4561(F).a
Figure 46. Block Diagram for the Transmit Facility Data Link Interface Transmit ANSI T1.403 Bit-Oriented Messages (BOM) When the ANSI BOM mode is enabled by setting register FDL_PR10 bit 7 to 1, the transmit FDL can send any of the ANSI T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame. The transmit ESF FDL bit-oriented messages of the form 111111110X0X1X2X3X4X50 are taken from the transmit ANSI FDL parameter register FDL_PR10 bit 0--bit 5. The ESF FDL bit-oriented messages will be repeated while register FDL_PR10 bit 7 (FTANSI) is set to 1.
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Facility Data Link (FDL) (continued)
Transmit ANSI Performance Report Messages (PRM) When the ANSI PRM mode is enabled by setting register FDL_PR1 bit 7 to 1, the transmit FDL assembles and transmits the ANSI performance report message once every second. After assembling the ANSI PRM message, the receive framer stores the current second of the message in registers FRM_SR62 and FRM_SR63 and transfers the data to the FDL transmit FIFO. After accumulating three seconds (8 bytes) of the message, the FDL transmit block appends the header and the trailer (including the opening and closing flags) to the PRM messages and transmits it to the framer for transmission to the line. Tables 51--53 show the complete format of the PRM HDLC packet.
HDLC Operation
HDLC operation is the default mode of operation. The transmitter accepts parallel data from the transmit FIFO, converts it to a serial bit stream, provides bit stuffing as necessary, adds the CRC-16 and the opening and closing flags, and sends the framed serial bit stream to the transmit framer. HDLC frames on the serial link have the following format. Table 55. HDLC Frame Format Opening Flag 01111110 User Data Field 8 bits Frame Check Sequence (CRC) 16 bits Closing Flag 01111110
All bits between the opening flag and the CRC are considered user data bits. User data bits such as the address, control, and information fields for LAPB or LAPD frames are fetched from the transmit FIFO for transmission. The 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits. Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing) The HDLC protocol recognizes three special bit patterns: flags, aborts, and idles. These patterns have the common characteristic of containing at least six consecutive ones. A user data byte can contain one of these special patterns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of these special patterns. Whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1, prior to transmission of the next bit. On the receive side, if five successive ones are detected followed by a 0, the 0 is assumed to have been inserted and is deleted (bit destuffing).
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL) (continued)
Flags* All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automatically sends two flags between frames. If the chip-configuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive frames with a shared flag; therefore, two successive flags will not share the intermediate 0. An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data byte with the CRC sequence and a closing flag. The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As mentioned above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and deletion. The HDLC receiver recognizes a single flag between frames as both a closing and opening flag. Aborts An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register FDL_PR3 bit 6 (FTABT). This causes the last byte written to the transmit FIFO to be replaced with the abort sequence upon transmission. Once a byte is tagged by a write to FTABT, it cannot be cleared by subsequent writes to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue.
When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the status of frame status byte (see Table 54) which is appended to the receive data queue. All subsequent bytes are ignored until a valid opening flag is received. Idles In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle. When the HDLC block receives 15 contiguous ones, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set. For transmission, the ones idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS control bit in register FDL_PR0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. A time-fill byte is sent when the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames are sent back-to-back otherwise. CRC-16 For given user data bits, 16 additional bits that constitute an error-detecting code (CRC-16) are added by the transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the ITU-T standard polynomial: x 16 + x 12 + x 5 + 1 The transmitter can be instructed to transmit a corrupted CRC by setting register FDL_PR2 bit 7 (FTBCRC) to 1. As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flipping the least significant bit of the transmitted CRC. The receiver performs the same calculation on the received bits after destuffing and compares the results to the received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch.
* Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two flags.
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Facility Data Link (FDL) (continued)
Transmit FDL FIFO Transmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The transmit FDL status register indicates how many additional bytes can be added to the transmit FIFO. The transmit FDL interrupt trigger level register FDL_PR3 bit 0--bit 5 (FTIL) can be programmed to tailor service time intervals to the system environment. The transmitter empty interrupt bit is set in the FDL interrupt status register FDL_SR0 bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register FDL_PR3 bit 0--bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. Overrunning the transmitter causes the last valid data byte written to be repeatedly overwritten, resulting in missing data in the frame. Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the transmitter has completed a frame, with a closing flag or an abort sequence, register FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1. Sending 1-Byte Frames Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte frames are subject to underrun aborts. One-byte frames cannot be aborted with FTABT. Placing the transmitter in ones-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not empty, then 1-byte frames present no problems.
Transmitter Underrun After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. Using the Transmitter Status and Fill Level The transmitter-interrupt level bits, register FDL_PR3 bit 0--bit 5, allow the user to instruct the FDL HDLC block to interrupt the host processor whenever the transmitter has a predetermined number of empty locations. The number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts. The transmitter status bits, register FDL_SR1, report the number of empty locations in the FDL transmitter FIFO. The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is set to 1 when the number of empty locations is less than or equal to the programmed empty level. FTED returns to 0 when the transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to determine when they can write to the FDL transmit FIFO.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL) (continued)
Transparent Mode
The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6 (FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed. In the transmit direction, the FDL HDLC takes data from the transmit FIFO and transmits that data exactly bit-for-bit on the TFDL interface. Transmit data is octetaligned to the first TFDLCK after the transmitter has been enabled. The bits are transmitted least significant bit first. When there is no data in the transmit FIFO, the FDL HDLC either transmits all ones, or transmits the programmed HDLC transmitter idle character (register FDL_PR5) if register FDL_PR9 bit 6 (FMATCH) is set to 1. To cause the transmit idle character to be sent first, the character must be programmed before the transmitter is enabled. The transmitter empty interrupt, register FDL_SR0 bit 1 (FTEM), acts as in the HDLC mode. The transmitterdone interrupt, register FDL_SR0 bit 0 (FTDONE), is used to report an empty FDL transmit FIFO. The FTDONE interrupt thus provides a way to determine transmission end. Register FDL_SR0 bit 2 (FTUNDABT) interrupt is not active in the transparent mode. In the receive direction, the FDL HDLC block loads received data from the RFDL interface directly into the receive FIFO bit-for-bit. The data is assumed to be least significant bit first. If FMATCH register FDL_PR9 bit 6 is 0, the receiver begins loading data into the receive FIFO beginning with the first RFDLCK detected after the receiver has been enabled. If the FMATCH bit
is set to 1, the receiver does not begin loading data into the FIFO until the receiver match character has been detected. The search for the receiver match character is in a sliding window fashion if register FDL_PR9 bit 4 (FALOCT) bit is 0 (align to octet), or only on octet boundaries if FALOCT is set to 1. The octet boundary is aligned relative to the first RFDLCK after the receiver has been enabled. The matched character and all subsequent bytes are placed in the receive FIFO. An FDL receiver reset, register FDL_PR1 bit 4 (FRR) = 1, causes the receiver to realign to the match character if FMATCH is set to 1. The receiver full (FRF) and receiver overrun (FROVERUN) interrupts in register FDL_SR0 act as in the HDLC mode. The received end of frame (FREOF) and receiver idle (FRIDL) interrupts are not used in the transparent mode. The match status (FMSTAT) bit is set to 1 when the receiver match character is first recognized. If the FMATCH bit is 0, the FMSTAT (FDL_PR9 bit 3) bit is set to 1 automatically when the first bit is received, and the octet offset status bits (FDL_PR9 bit 0--bit 2) read 000. If the FMATCH bit is programmed to 1, the FMSTAT bit is set to 1 upon recognition of the first receiver match character, and the octet offset status bits indicate the offset relative to the octet boundary at which the receiver match character was recognized. The octet offset status bits have no meaning until the FMSTAT bit is set to 1. An octet offset of 111 indicates byte alignment. An interrupt for recognition of the match character can be generated by setting the FRIL level to 1. Since the matched character is the first byte written to the FIFO, the FRF interrupt occurs with the writing of the match character to the receive FIFO. Programming Note: The match bit (FMATCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle character and the receive match character before setting FMATCH. If the transmit idle character is programmed to FF (hex), the FMATCH bit appears to affect only the receiver.
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Facility Data Link (FDL) (continued)
The operation of the receiver in transparent mode is summarized in Table 56. Table 56. Receiver Operation in Transparent Mode FALOCT X 0 1 FMATCH 0 1 1 Receiver Operation Serial-to-parallel conversion begins with first RFDLCK after FRE, register FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately. Match user-defined character using sliding window. Byte aligns once character is recognized. No data to receive FIFO until match is detected. Match user-defined character, but only on octet boundary. Boundary based on first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO until match is detected.
Diagnostic Modes
Loopbacks The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. The local loopback mode is selected when register FDL_PR1 bit 1 (FLLB) is set to 1. The remote loopback is selected when register FDL_PR1 bit 0 (FRLB) is set to 1. For normal traffic, i.e., to operate the transmitter and receiver independently, the FLLP bit and the FRLB bits should both be cleared to 0. Local and remote loopbacks cannot be enabled simultaneously. In the local loopback mode:
s s s s s s
TFDLCK clocks both the transmitter and the receiver. The transmitter and receiver must both be enabled. The transmitter output is internally connected to the receiver input. The TFDL is active. The RFDL input is ignored. The communication between the transmit and receive FIFO buffers and the microprocessor continues normally.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Facility Data Link (FDL) (continued)
XMIT HDLC FDL BLOCK
XMIT FIFO
XMIT HDLC
FDL XMIT INTERFACE
TFDL TFDLCK
RCVR FIFO
RCVR HDLC
FDL RCVR INTERFACE RFDL
RFDLCK
RCVR HDLC FDL BLOCK
5-4562(F)r.2
Figure 47. Local Loopback Mode
In the remote loopback mode:
s s s
Transmitted data is retimed with a maximum delay of 2 bits. Received data is retransmitted on the TFDL. The transmitter should be disabled. The receiver can be disabled or enabled. Received data is sent as usual to the receive FIFO if the receiver is denabled.
XMIT HDLC FDL BLOCK TFDL XMIT FIFO XMIT HDLC FDL XMIT INTERFACE
TFDLCK
RFDLCK RCVR FIFO RCVR HDLC FDL RCVR INTERFACE RFDL RCVR HDLC FDL BLOCK
5-4563(F)r.1
Figure 48. Remote Loopback Mode
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Phase-Lock Loop Circuit
The T7630 allows for independent transmit path and receive path clocking. The device provides outputs to control variable clock oscillators on both the transmit and receive paths. As such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. The block diagram of the T7630 phase detector circuitry is shown in Figure 49. The T7630 uses elastic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2.048 Mbits/s to the line interface clock rate of either 1.544 Mbits/s or 2.048 Mbits/s. The transmit line side of the T7630 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This interface relies on the requirement that the PLLCK clock signal (variable) is phase-locked to the RCHICK clock signal (reference). When this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result in corrupting data and no indication will be given. Typically, a variable clock oscillator (VCXO) is used to drive the PLLCK signal. The T7630 provides a phase error signal (PLLCK-EPLL) that can be used to control the VCXO. The PLLCK-EPLL signal is generated by monitoring the divided-down PLLCK (DIV-PLLCK) and RCHICK (DIV-RCHICK) signals. The DIV-RCHICK signal is used as the reference to determine the phase difference between DIV-RCHICK and DIV-PLLCK. While DIV-RCHICK and DIVPLLCK are phase-locked, the PLLCK-EPLL signal is in a high-impedance state. A phase difference between DIV-RCHICK and DIVPLLCK drives PLLCK-EPLL to either 5 V or 0 V. An appropriate loop filter, for example, an RC circuit with R = 1 k and C = 0.1 F) is used to filter these PLLCKEPLL pulses to control the VCXO.
The system can force TCHICK to be phase-locked to RLCK by using RLCK as a reference signal to control a VCXO that is sourcing the TCHICK signal. The T7630 uses the receive line signal (RLCK) as the reference and the TCHICK signal as the variable signal. The T7630 provides a phase error signal (TCHICK-EPLL) that can be used to control the VCXO generating TCHICK. The TCHICK-EPLL signal is generated by monitoring the divided-down TCHICK signal (DIV-TCHICK) and RLCK (DIV-RLCK) signals. The DIV-RLCK signal is used as the reference to determine the phase difference between DIV-TCHICK and DIV-RLCK. While DIVRLCK and DIV-TCHICK are phase-locked, the TCHICK-EPLL signal is in a high-impedance state. A phase difference between DIV-RLCK and DIV-TCHICK drives TCHICK-EPLL to either 5 V or 0 V. An appropriate loop filter, for example, an RC circuit with R = 1 k and C = 0.1 F, is used to filter these TCHICK-EPLL pulses to control the VCXO. In this mode, the T7630 can be programmed to act as a master timing source and is capable of generating the system frame synchronization signal through the TCHIFS pin by setting FRM_PR45 bit 4 to 1.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Phase-Lock Loop Circuit (continued)
EXTERNAL CIRCUIT VOLTAGECONTROLLED CRYSTAL OSCILLATOR (VCXO)
PLLCK
DIV-PLLCK
PLLCK-EPLL
DIV-RCHICK
PLLCK DIVIDER CIRCUIT INTERNAL_XLCK
DIGITAL PHASE DETECTOR
RCHICK DIVIDER CIRCUIT
INTERNAL_RCHICK RCHICK TLCK TRANSMIT FRAMER TPD, TND
FACILITY DATA READ ADDRESS
TRANSMIT 2-FRAME ELASTIC STORE BUFFER
WRITE ADDRESS
SYSTEM DATA
RECEIVE CONCENTRATION HIGHWAY INTERFACE
RCHIFS RCHIDATA
BUFFER OVERRUN BUFFER UNDERRUN
SLIP MONITOR
RPD, RND RLCK RECEIVE FRAMER
WRITE ADDRESS
FACILITY DATA
RECEIVE 2-FRAME ELASTIC STORE BUFFER
READ ADDRESS
SYSTEM DATA
TRANSMIT CONCENTRATION HIGHWAY INTERFACE
TCHIDATA TCHIFS TCHICK
INTERNAL_RLCK RLCK DIVIDER CIRCUIT DIV-RLCK DIGITAL PHASE DETECTOR TCHICK_EPLL
INTERNAL_TCHICK TCHICK DIVIDER CIRCUIT DIV-TCHICK
VOLTAGECONTROLLED CRYSTAL OSCILLATOR (VCXO) EXTERNAL CIRCUIT
5-5268(F)r.2
Figure 49. T7630 Phase Detector Circuitry
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Framer-System (CHI) Interface
DS1 Modes
The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 DS1 (1.544 Mbits/s) payload time slots while there are 32 system (2.048 Mbits/s) time slots. Placement of the stuffed time slots is defined by register FRM_PR43 bit 0--bit 2.
Concentration Highway Interface
Each framer has a dual, high-speed, serial interface to the system known as the CHI. This flexible bus architecture allows the user to directly interface to other Lucent components which use this interface, as well as to Mitel * and AMD TDM highway interfaces, with no glue logic. Configured via the highway control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configurations. The following is a list of the CHI features:
s
Lucent Technologies standard interface for communication devices. Two pairs of transmit and receive paths to carry data in 8-bit time slots. Programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. Programmable idle code substitution of received time slots. Programmable 3-state control of each transmit time slot. Independent transmit and receive framing signals to synchronize each direction of data flow. An 8 kHz frame synchronization signal internally generated from the received line clock. Compatible with Mitel and AMD PCM highways.
CEPT Modes
The framer maps the line time slots into the corresponding system time slot one-to-one. Framing time slot 0, the FAS and NFAS bytes, are placed in system time slot 0.
s
s
s
Receive Elastic Store
The receive interface between the framer and the system (CHI) includes a two-frame elastic store buffer to enable rate adaptation. The receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. Whenever this slip circuitry determines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a controlled slip is performed. The controlled slip is implemented by dropping or repeating a complete frame at the frame boundaries. The occurrence of controlled slips in the receive elastic store are indicated in the status register FRM_SR3 bit 6 and bit 7.
s
s
s
s
Supported is the optional configuration of the CHI which presents the signaling information along with the data in any framing modes when the device is programmed for the associated signaling mode (ASM). This mode is discussed in the signaling section. Data can be transmitted or received on either one of two interface ports, called CHIDATA and CHIDATAB. The user-supplied clocks (RCHICLK and TCHICLK) control the timing on the transmit or receive paths. Individual time slots are referenced to the frame synchronization (RCHIFS and TCHIFS) pulses. Each frame consists of 32 time slots at a programmable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s requiring a clock (TCHICK and RCHICK) of the same rate. The clock and data rates of the transmit and receive highways are programmed independently.
Transmit Elastic Store
The transmit interface between the framer and the system (CHI) includes a two-frame elastic store buffer to enable rate adaptation. The line transmit clock applied to PLLCK (pins 7/31) must be phase-locked to RCHICK. No indication of a slip in the transmit elastic store is given.
* Mitel is a registered trademark of Mitel Corporation. AMD is a registered trademark of Advanced Micro Devices, Inc.
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Concentration Highway Interface (continued)
Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s, 4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is achieved by means of stuffing eight idle time slots into the existing twenty-four time slots of the T1 frame. Idle time slots can occur every fourth time slot (starting in the first, second, third, or fourth time slot) or be grouped together at the end of the CHI frame as described in register FRM_PR43 bit 0--bit 2. The positioning of the idle time slots is the same for transmit and receive directions. Idle time slots contain the programmable code of register FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA interface to a high-impedance state for the interval of the disabled time slots.
CHI Parameters
The CHI parameters that define the receive and transmit paths are given in Table 57. Table 57. Summary of the T7630's Concentration Highway Interface Parameters Name HWYEN Description Highway Enable (FRM_PR45 bit 7). A 1 in this bit enables the transmit and receive concentration highway interfaces. This allows the framer to be fully configured before transmission to the highway. A 0 forces the idle code as defined in register FRM_PR22, to be transmitted to the line in all payload time slots while TCHIDATA is forced to a high-impedance state for all CHI transmitted time slots. Concentration Highway Master Mode (PRM_PR45 bit 4). The default mode CHIMM = 0 enables an external system frame synchronization signal (TCHIFS) to drive the transmit CHI. A 1 enables the transmit CHI to generate a system frame synchronization signal from the receive line clock. The transmit CHI system frame synchronization signal is generated on the TCHIFS output pin. Applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the TCHIFS signal generated by the framer. The receive CHI path is not affected by this mode. CHI Double Time-Slot Mode (FRM_PR65 bit 1 and FRM_PR66 bit 1). CHIDTS defines the 4.096 Mbits/s and 8.192 Mbits/s CHI modes. CHIDTS = 0 enables the 32 contiguous time-slot mode. This is the default mode. CHIDTS = 1 enables the double time-slot mode in which the transmit CHI drives TCHIDATA for one time slot and then 3-states for the subsequent time slot, and the receive CHI latches data from RCHIDATA for one time slot and then ignores the following time slot and so on. CHIDTS = 1 allows two CHIs to interleave frames on a common bus. Transmit Frame Edge (FRM_PR46 bit 3). TFE = 0 (or 1), TCHIFS is sampled on the falling (or rising) edge of TCHICK. In CHIMM (CHI master mode), the TCHIFS pin outputs a transmit frame strobe to provide synchronization for TCHIDATA. When TFE = 1 (or 0), TCHIFS is centered around rising (or falling) edge of TCHICK. In this mode, TCHIFS can be used for receive data on RCHIDATA. The timing for TCHIFS in CHIMM = 1 mode is identical to the timing for TCHIFS in CHIMM = 0 mode. Receive Frame Edge (FRM_PR46 bit 7). RFE = 0 (or 1), RCHIFS is sampled on the falling (or rising) edge of RCHICK. CHI Data Rate (FRM_PR45 bit 2 and bit 3). Two-bit control for selecting the CHI data rate. The default state (00) enables the 2.048 Mbits/s. CDRS Bit:2 3CHI Data Rate 0 0 2.048 Mbits/s 0 1 4.096 Mbits/s 1 0 8.192 Mbits/s 1 1 Reserved 113
CHIMM
CHIDTS
TFE
RFE CDRS0--CDRS1
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Concentration Highway Interface (continued)
Table 57. Summary of the T7630's Concentration Highway Interface Parameters (continued) Name TCE RCE TTSE31--TTSE0 Description Transmitter Clock Edge (FRM_PR47 bit 6). TCE = 0 (or 1), TCHIDATA is clocked on the falling (or rising) edge of TCHICK. Receiver Clock Edge (FRM_PR48 bit 6). RCE = 0 (or 1), RCHIDATA is latched on the falling (or rising) edge of RCHICK. Transmit Time-Slot Enable 31--0 (FRM_PR49--FRM_PR52). These bits define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. Receive Time-Slot Enable 31--0 (FRM_PR53--FRM_PR56). These bits define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHDATAB time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to the line interface. Transmit Highway Select 31--0 (FRM_PR57--FRM_PR60). These bits define which transmit CHI highway, TCHIDATA or TCHIDATAB, contains valid data for the active time slot. A 0 enables TCHIDATA; a 1 enables the TCHIDATAB. Receive Highway Select 31--0 (FRM_PR61--FRM_PR64). These bits define which receive CHI highway, RCHIDATA or RCHIDATAB, contains valid data for the active time slot. A 0 enables RCHIDATA; a 1 enables the RCHIDATAB. Transmitter Bit Offset (FRM_PR46 bit 0--bit 2). These bits are used in conjunction with the transmitter byte offset to define the beginning of the transmit frame. They determine the offset relative to TCHIFS, for the first bit of transmit time slot 0. The offset is the number of TCHICK cycles by which the first bit is delayed. Receiver Bit Offset (FRM_PR46 bit 4--bit 6). These bits are used in conjunction with the receiver byte offset to define the beginning of the receiver frame. They determine the offset relative to the RCHIFS, for the first bit of receive time slot 0. The offset is the number of RCHICK cycles by which the first bit is delayed. Transmitter Byte Offset (FRM_PR47 bit 0--bit 5 and FRM_PR65 bit 0). These bits determine the offset from the TCHIFS to the beginning of the next frame on the transmit highway. Note that in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets: 2.048 Mbits/s 0--31 bytes. 4.096 Mbits/s 0--63 bytes. 8.192 Mbits/s 0--127 bytes. Receiver Byte Offset (FRM_PR48 bit 0--bit 5 and FRM_PR66 bit 0). These bits determine the offset from RCHIFS to the beginning of the receive CHI frame. Note that in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets: 2.048 Mbits/s 0--31 bytes. 4.096 Mbits/s 0--63 bytes. 8.192 Mbits/s 0--127 bytes. Associated Signaling Mode (FRM_PR44 bit 2). When enabled, the associate signaling mode configures the CHI to carry both payload data and its associated signaling information. Enabling this mode must be in conjunction with the programming of the CHI data rate to either 4.048 Mbits/s or 8.096 Mbits/s. Each time slot consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. Stuffed Time Slots (FRM_PR43 bit 0--bit 2). Valid only in T1 framing formats, these 3 bits define the location of the eight stuffed CHI (unused) time slots.
RTSE31--RTSE0
THS31--THS0
RHS31--RHS0
TOFF2--TOFF0
ROFF2--ROFF0
TBYOFF6--TBYOFF0
RBYOFF6--RBYOFF0
ASM
STS0--STS2
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Concentration Highway Interface (continued)
CHI Frame Timing
CHI Timing with CHIDTS Disabled Figure 50 illustrates the CHI frame timing when CHIDTS is disabled (registers FRM_PR65 bit 1 (TCHIDTS) and FRM_PR66 bit 1 (RCHDTS) = 0) and the CHI is not in the associated signaling mode (FRM_PR44 bit 2 (ASM) = 0). The frames are 125 s long and consist of 32 contiguous time slots. In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. In CEPT frame modes, the CHI frame consists of 32 payload time slots.
125 s
CHIFS DS1 FORMAT 2.048 Mbits/s CHI: TCHIDATA
FRAME 1 24 VALID TIME SLOTS HIGH IMPEDANCE 8 STUFFED SLOTS* FRAME 2
RCHIDATA CEPT FORMAT 2.048 Mbits/s CHI:
24 VALID TIME SLOTS
FRAME 2
32 VALID TIME SLOTS TCHIDATA or RCHIDATA FRAME 1 FRAME 2
4.096 Mbits/s CHI: HIGH IMPEDANCE
TCHIDATA
FRAME 1
FRAME 2
RCHIDATA
FRAME 1
FRAME 2
8.192 Mbits/s CHI: TCHIDATA FRAME 1 HIGH IMPEDANCE FRAME 2
RCHIDATA
FRAME 1
FRAME 2
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* The position of the stuffed time is controlled by register FRM_PR43 bit 0--bit 2.
Figure 50. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0--bit 2 = 100 (Binary))
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Concentration Highway Interface (continued)
CHI Timing with CHIDTS Enabled Figure 51 illustrates the CHI frame timing when CHIDTS is enabled (registers FRM_PR65 bit 1 (TCHIDTS) and FRM_PR66 bit 1 (RCHIDTS) = 1) and ASM is disabled (register FRM_PR44 bit 2 (ASM) = 0). In the CHIDTS mode, valid CHI payload time slots are alternated with high-impedance intervals of one time-slot duration. This mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI rates.
125 s
CHIFS
4.096 Mbits/s CHI
TIME TIME SLOT SLOT
FRAME 1
FRAME 2
TCHIDATA
TS0 8 bits
TS1
TS2
TS3
TS4
TS30
TS31
TS0
RCHIDATA
TS0
TS1
TS2
TS3
TS4
T30
TS31
TS0
8.192 Mbits/s CHI TCHIDATA
TS0 TS1 TS2 TS30 TS31
HIGH IMPEDANCE
TS0
RCHIDATA
TS0
TS1
TS2
TS30
TS31
TS0
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Figure 51. CHIDTS Mode Concentration Highway Interface Timing
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Concentration Highway Interface (continued)
CHI Timing with Associated Signaling Mode Enabled Figure 52 illustrates the CHI frame timing when the associated signaling mode is enabled (register FRM_PR44 bit 2 (ASM) = 1) and the CHIDTS mode is disabled (registers FRM_PR65 bit 1 (TCHIDTS) = 0 and FRM_PR66 bit 1 (RCHDTS) = 0). The frames are 125 s long and consist of 32 contiguous 16-bit time slots. In DS1 frame formats, each frame consists of 24 time slots and eight stuffed time slots. Each time slot consists of two octets. In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets.
125 s
CHIFS 4.096 Mbits/s CHI: TCHIDATA or RCHIDATA FRAME = 64 bytes: 32 DATA + 32 SIGNALING FRAME 1 FRAME 2
DATA AND SIGNALING BYTES ARE INTERLEAVED DATA 0 SIGNALING 0 DATA 31 SIGNALING 31 DATA 0
FRAME 8.192 Mbits/s CHI: HIGH IMPEDANCE TCHIDATA FRAME 1 FRAME 2
RCHIDATA FRAME 1 FRAME 2
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Figure 52. Associated Signaling Mode Concentration Highway Interface Timing CHI Timing with Associated Signaling Mode and CHIDTS Enabled Figure 53 illustrates the CHI frame timing in the associated signaling mode (register FRM_PR44 bit 2 (ASM) = 1) and CHIDTS enabled (registers FRM_PR65 bit 1 (TCHIDTS) = 1 and FRM_PR66 bit 1 (RCHIDTS) = 1).
8.192 Mbits/s CHI WITH ASM (ASSOCIATED SIGNALING MODE) ENABLED
TS0 TCHIDATA OR RCHIDATA TS1 TS31 TS0
*
DATA
SIGNALING
*
*
DATA
SIGNALING
16 bits 1 TIME SLOT
16 bits 1 TIME SLOT
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* High-impedance state for TCHIDATA and not received (don't care) for RCHIDATA.
Figure 53. CHI Timing with ASM and CHIDTS Enabled Lucent Technologies Inc. Lucent Technologies Inc. 117
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Concentration Highway Interface (continued)
CHI Offset Programming
To facilitate bit offset programming, two additional internal parameters are introduced: CEX is defined as the clock edge with which the first bit of time slot 0 is transmitted; CER is defined as the clock edge on which bit 0 of time slot 0 is latched. CEX and CER are counted relative to the edge on which the CHIFS signal is sampled. Values of CEX and CER depend upon the values of the parameters described above. The following table gives decimal values of CEX and CER for various values of TFE, RFE, TCE, RCE, TOFF[2:0], and ROFF[2:0]. The byte (time slot) offsets are assumed to be zero in the following examples. Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 RFE/ TFE 0 0 1 1 RCE/ TCE 0 1 0 1 ROFF[2:0] or TOFF[2:0] 000 4 3 3 4 001 6 5 5 6 010 8 7 7 8 011 10 9 9 10 100 12 11 11 12 101 14 13 13 14 110 16 15 15 16 111 18 17 17 18 CER or CEX (decimal)
Figure 54 shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:
s s s
CMS = 0, TFE, RFE = 0 TCE = 1, TOFF[2:0] = 000, TBYOFF[6:0] = 0000000 RCE = 0, ROFF[2:0] = 000, RBYOFF[6:0] = 0000000
CHIFS IS SAMPLED ON THIS EDGE: FE = 0 1 2 3 4 5 6 7 8
CHICK
TCHIFS, RCHIFS
CEX = 3 TCHIDATA: TCE = 1 HIGH IMPEDANCE BIT 0, TS 0 CER = 4 RCHIDATA: RCE = 0 BIT 0, TS 0 BIT 1, TS 0 BIT 2, TS 0
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BIT 1, TS 0
BIT 2, TS 0
Figure 54. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 (CEX = 3 and CER = 4, Respectively)
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Concentration Highway Interface (continued)
Figures 55 and 56 illustrate the CHI timing.
RCHICLK t14S t14H t14S: RCHIFS SETUP = 30 ns min t14H: RCHIFS HOLD = 45 ns min RCHIFS
t15S RCHIDATA
t15H t15S: RCHIDATA SETUP = 25 ns min t15S: RCHIDATA HOLD = 25 ns min
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Note: For case illustrated, RFE = 0, and RCE = 0.
Figure 55. Receive CHI (RCHIDATA) Timing
TCHICLK t14S t14H t14S: TCHIFS SETUP = 35 ns min t14H: TCHIFS HOLD = 45 ns min TCHIFS
t19 TCHIDATA
t19: TCHICK TO TCHIDATA DELAY = 25 ns max
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Note: For case illustrated, TFE = 0 and TCE = 0.
Figure 56. Transmit CHI (TCHIDATA) Timing
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JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:
s s s
Testing the connections between ICs on a particular board. Observation of signals to the IC pins during normal operating functions. Controlling the built-in self-test (BIST) of an IC. T7630 does not support BS-BIST.
Designed according to the IEEE* Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller, an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and DCODE register). The main component is the BS register that links all the chip pins to a shift register by means of special logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the T7630 (the mode multiplexer of the BS output cells may be shared). Figure 57 illustrates the block diagram of the T7630's BS test logic.
BOUNDARY-SCAN REGISTER
CHIP KERNEL IN OUT
(UNAFFECTED BY BOUNDARY-SCAN TEST)
IDCODE REGISTER
BYPASS REGISTER TDI INSTRUCTION REGISTER TRST
MUX
TDO
TMS TCK TAP CONTROLLER
INSTRUCTION DECODER
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Figure 57. Block Diagram of the T7630's Boundary-Scan Test Logic
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
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JTAG Boundary-Scan Specification (continued)
Test Access Port Controller
The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST signals and by the previous state. The state change always take place when the TCK edge rises. Figure 58 shows the TAP controller state diagram.
TRST = 0
TEST LOGIC RESET 1 0 RUN TEST/ IDLE 0 1 1 SELECT-DR 0 CAPTURE-DR 0 SHIFT-DR 0 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 1 1 EXIT1-IR 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 0 0 1 1 SELECT-IR 0 CAPTURE-IR 0 SHIFT-IR 0 1
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Figure 58. BS TAP Controller State Diagram The value shown next to each state transition in Figure 58 represents the signal present at TMS at the time of a rising edge at TCK. The description of the TAP controller states is given in IEEE Std. 1149.1-1990 Section 5.1.2 and is reproduced in Tables 59 and 60.
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JTAG Boundary-Scan Specification (continued)
Table 59. TAP Controller States in the Data Register Branch Name TEST LOGIC RESET Description The BS logic is switched in such a way that normal operation of the ASIC is adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET. Irrespective of the initial state, the TAP controller has achieved TEST LOGIC RESET after five control pulses at the latest when TMS = 1. The TAP controller then remains in this state. This state is also achieved when TRST = 0. Using the appropriate instructions, this state can activate circuit parts or initiate a test. All of the registers remain in their present state if other instructions are used. This state is used for branching to the test data register control. The test data is loaded in the test data register parallel to the rising edge of TCK in this state. The test data is clocked by the test data register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of test data can be interrupted in this state. The test data is clocked into the second stage of the test data register parallel to the falling edge of TCK in this state.
RUN TEST/IDLE
SELECT DR CAPTURE DR SHIFT DR EXIT (1/2) DR PAUSE DR UPDATE DR
Table 60. TAP Controller States in the Instruction Register Branch Name SELECT IR CAPTURE IR SHIFT IR EXIT (1/2) IR PAUSE IR UPDATE IR Description This state is used for branching to the instruction register control. The instruction code 0001 is loaded in the first stage of the instruction register parallel to the rising edge of TCK in this state. The instructions are clocked into the instruction register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of instructions can be interrupted in this state. The instruction is clocked into the second stage of the instruction register parallel to the falling edge of TCK in this state.
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JTAG Boundary-Scan Specification (continued)
Instruction Register
The instruction register (IR) is 4 bits in length. Table 61 shows the BS instructions implemented by the T7630. Table 61. T7630's Boundary-Scan Instructions Instruction EXTEST IDCODE HIGHZ SAMPLE/PRELOAD BYPASS EVERYTHING ELSE Code 0000 0001 0100 0101 1111 -- Act. Register TDI--TDO Boundary Scan Identification BYPASS Boundary Scan BYPASS BYPASS Mode TEST NORMAL X NORMAL NORMAL X HIGHZ All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports to an input state by means of the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE-IR state. The function outputs are only determined in accordance with another instruction if a different instruction becomes active in the UPDATE-IR state. The BYPASS register is selected as the test data register. The HIGHZ instruction is implemented in a similar manner to that used for the BYPASS instruction. SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction enables all the inputs and outputs pins to be sampled during operation (SAMPLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions. Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD). Function Test external connections Read Manuf. Register 3-state Sample/load Min. shift path -- Output Defined Via BS Register Core Logic Output--High Impedance Core Logic Core Logic Output--High Impedance
The instructions not supported in T7630 are INTEST, RUNBIST, and TOGGLE. A fixed binary 0001 pattern (the 1 into the least significant bit) is loaded into the IR in the capture-IR controller state. The IDCODE instruction (binary 0001) is loaded into the IR during the testlogic-reset controller state and at powerup. The following is an explanation of the instructions supported by T7630 and their effect on the devices' pins. EXTEST This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRELOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE-DR state. The contents of the BS register can be clocked out via TDO in the SHIFT-DR state. The value of the function outputs is solely determined by the contents of the data clocked into the BS register and only changes in the UPDATE-DR state on the falling edge of TCK. IDCODE Information regarding the manufacturer's ID for Lucent, the IC number, and the version number can be read out serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal mode in the UPDATE-IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTUREDR state. The IDCODE register is read out via TDO in the SHIFT-DR state. Lucent Technologies Inc. Lucent Technologies Inc.
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JTAG Boundary-Scan Specification (continued)
BYPASS This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS register is selected after the UPDATE-IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register during CAPTURE-DR state. Data can be shifted by the BYPASS register during SHIFT-DR. The contents of the BS register do not change in the UPDATE-DR state. Please note that a 0 that was loaded during CAPTURE-DR appears first when the data is being read out.
Boundary-Scan Register
The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital T7630 pin (with the exception of the pins for the BS architecture, analog signals, and supply voltages). The T7630's boundary-scan register bit-to-pin assignment is to be determined.
BYPASS Register
The BYPASS register is a one-stage, shift register that enables the shift chain to be reduced to one stage in the T7630.
IDCODE Register
The IDCODE register identifies the T7630 by means of a parallel, loadable, 32-bit shift register. The code is loaded on the rising edge of TCK in the CAPTURE-DR state. The 32-bit data is organized into four sections as follows. Table 62. IDCODE Register Version Bits 31--28 0001 Part Number Bits 27--12 0111 011000110000 Manufacturer ID Bits 11--1 0000 0011101 1 Bit 0 1
3-State Procedures
The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update pattern at the T7630 outputs does not become corrupted.
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registers, the INTERRUPT output will deassert. In the polled mode, however, the microprocessor monitors the various device alarm status by periodically reading the alarm status registers within the line interface unit, framer, and HDLC blocks without the use of INTERRUPT. In both interrupt and polled methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle only when the alarm condition within that block no longer exists; otherwise, the alarm status register bit remains set. The powerup default states for the line interface unit, framer, and the HDLC blocks are discussed in their respective sections. All read/write registers within these blocks must be written by the microprocessor on system start-up to guarantee proper device functionality. Register addresses not defined in this data sheet must not be written. Details concerning the microprocessor interface configuration modes, pinout definitions, clock specifications, register address map, I/O timing specifications, and the I/O timing diagrams are described in the following sections.
Microprocessor Interface
Overview
The T7630 device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. The microprocessor interface provides access to all the internal registers through a 12-bit address bus and an 8-bit data bus. Inputs MPMODE and MPMUX (pins 74 and 76) are used to configure this interface into one of four possible modes, as shown in Table 63. The MPMUX setting selects either a multiplexed (8-bit address/data bus, AD[7:0]) or a demultiplexed (12-bit address bus, A[11:0] and an 8-bit data bus AD[7:0]) mode of operation. The MPMODE setting selects the associated set of control signals required to access a set of registers within the device. The microprocessor interface can operate at speeds up to 33 MHz in interrupt-driven or polled mode without requiring any wait-states. For microprocessors operating at greater than 33 MHz, the RDY_DTACK output (pin 100) may be used to introduce wait-states in the read/write cycles. In the interrupt-driven mode, one or more device alarms will assert the INTERRUPT output (pin 99) once per alarm activation. After the microprocessor identifies the source(s) of the alarm(s) (by reading the global interrupt register) and reads the specific alarm status Table 63. Microprocessor Configuration Modes Mode Mode 1 Mode 2 Mode 3 Mode 4 MPMODE 0 0 1 1 MPMUX 0 1 0 1
Microprocessor Configuration Modes
Table 63 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs (pins 76 and 74).
Address/Data Bus DEMUXed* MUXed DEMUXed* MUXed
Generic Control, Data, and Output Pin Names
CS, AS, DS, R/W, A[11:0], AD[7:0], INT, DTACK CS, AS, DS, R/W, A[11:8], AD[7:0], INT, DTACK CS, ALE, RD, WR, A[11:0], AD[7:0], INT, RDY CS, ALE, RD, WR, A[11:8], AD[7:0], INT, RDY
* ALE_AS may be connected to ground in this mode. The DTACK signal is asynchronous to the MPCLK signal.
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Microprocessor Interface (continued)
Microprocessor Interface Pinout Definitions
The Mode [1--4] specific pin definitions are given in Table 64. Note that the microprocessor interface uses the same set of pins in all modes. Table 64. Mode [1--4] Microprocessor Pin Definitions
Configuration Mode 1 Pin Number 107 75 Device Pin Name WR_DS RD_R/W Generic Pin Name DS R/W Pin_Type Input Input Assertion Sense Active-Low -- Function Data Strobe Read/Write R/W = 1 => Read R/W = 0 => Write Address Strobe Chip Select Interrupt Data Acknowledge Data Bus Address Bus Microprocessor Clock Data Strobe Read/Write R/W = 1 => Read R/W = 0 => Write Address Strobe Chip Select Interrupt Data Acknowledge Address/Data Bus Address/Data Bus Microprocessor Clock Write Read Address Latch Enable Chip Select Interrupt Ready Data Bus Address Bus Microprocessor Clock Write Read Address Latch Enable Chip Select Interrupt Ready Address/Data Bus Address/Data Bus Microprocessor Clock
77 78 99 100 86--79 98--87 101 Mode 2 107 75
ALE_AS CS INTERRUPT RDY_DTACK AD[7:0] A[11:0] MPCLK WR_DS RD_R/W
AS CS INTERRUPT* DTACK AD[7:0] A[11:0] MPCLK DS R/W
Input Input Output Output I/O Input Input Input Input
Active-Low Active-Low Active-High/ Low Active-Low -- -- -- Active-Low --
77 78 99 100 86--79 98--87 101 Mode 3 107 75 77 78 99 100 86--79 98--87 101 Mode 4 107 75 77 78 99 100 86--79 98--87 101
ALE_AS CS INTERRUPT RDY_DTACK AD[7:0] A[11:8], AD[7:0] MPCLK WR_DS RD_R/W ALE_AS CS INTERRUPT RDY_DTACK AD[7:0] A[11:0] MPCLK WR_DS RD_R/W ALE_AS CS INTERRUPT RDY_DTACK AD[7:0] A[11:8], AD[7:0] MPCLK
AS CS INTERRUPT* DTACK AD[7:0] A[11:8], AD[7:0] MPCLK WR RD ALE CS INTERRUPT* RDY AD[7:0] A[11:0] MPCLK WR RD ALE CS INTERRUPT* RDY AD[7:0] A[11:8], AD[7:0] MPCLK
Input Input Output Output I/O Input Input Input Input Input Input Output Output I/O Input Input Input Input Input Input Output Output I/O Input Input
-- Active-Low Active-High/Low Active-Low -- -- -- Active-Low Active-Low Active-Low Active-Low Active-High/Low Active-High -- -- -- Active-Low Active-Low -- Active-Low Active-High/Low Active-High -- -- --
* INTERRUPT output is synchronous to the internal clock source RLCK-LIU. If RLCK_LIU is absent, the reference clock for interrupt timing becomes an interval 2.048 MHz clock derived from the CHI clock. The DTACK output is asynchronous to MPCLK. MPCLK is needed if RDY output is required to be synchronous to MPCLK. In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Microprocessor Interface (continued)
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 33 MHz without requiring any waitstates. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock (MPCLK, pin 101) specification is shown in Table 65. This clock must be supplied only if the RDY (MODE 3 and MODE 4) is required to be synchronous to MPCLK. Table 65. Microprocessor Input Clock Specifications Name MPCLK Symbol t1 Period and Tolerance 30 to 323 Trise Typ 2 Tfall Typ 2 Duty Cycle Min High 12 Min Low 12 ns Unit
Microprocessor Interface Register Address Map
The register address space is divided into eight contiguous banks of 512 addressable units each. Each addressable unit is an 8-bit register. These register banks are labeled as REGBANK[7:0]. The register address map table gives the address range of these register banks and their associated circuit blocks. REGBANK0 contains the global registers which are common to all the circuit blocks on T7630. REGBANK1 is reserved and must not be written. REGBANK[2, 5] are attached to the LIU circuit blocks. REGBANK[3, 6] are attached to the framer circuit blocks. REGBANK[4, 7] are attached to the FDL circuit blocks. The descriptions of the individual register banks can be found in the appropriate sections of this document. In these descriptions, all addresses are given in hexadecimal. Addresses out of the range specified by Table 66 must not be addressed. If they are written, they must be written to 0. An inadvertant write to an out-of-range address may be corrected by a device reset. Table 66. T7630 Register Address Map Register Bank Label Start Address End Address (in Hex) (in Hex) REGBANK0 REGBANK1 REGBANK2 REGBANK3 REGBANK4 REGBANK5 REGBANK6 REGBANK7 000 -- 400 600, 6E0 800 A00 C00, CE0 E00 007 -- 406 6A6, 6FF 80E A06 CA6, CFF E0E Circuit Block Name T7630 Global Registers* Reserved Line Interface Unit 1 (LIU1) Framer1 Facility Data Link 1 (FDL1) Line Interface Unit 2 (LIU2) Framer2 Facility Data Link 2 (FDL2)
* Core registers are common to all circuit blocks on T7630.
I/O Timing
The I/O timing specifications for the microprocessor interface are given in Table 67. The microprocessor interface pins are compatible with CMOS/TTL I/O levels. All outputs, except the address/data bus AD[7:0], are rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load.
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Microprocessor Interface (continued)
In modes 1 and 3, asserting ALE_AS signal low is used to enable the internal address bus. In modes 2 and 4, the falling edge of ALE_AS signal is used to latch the address bus. Table 67. Microprocessor Interface I/O Timing Specifications Symbol Configuration Parameter Setup (ns) (Min) -- 10 -- -- 4 0 -- -- -- -- -- -- -- -- -- 10 10 -- -- -- 10 -- 0 10 10 5 -- -- 5 10 10 -- 10 -- -- -- Hold (ns) (Min) 10 -- 10 -- -- -- -- -- -- -- 5 5 -- Delay (ns) (Max) -- -- -- -- -- -- 12 15 15 25 -- -- 12 10 -- -- -- -- -- -- -- -- -- -- --
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25
Modes 1 & 2
AS Asserted Width Address Valid to AS Deasserted AS Deasserted to Address Invalid -- R/W Valid to Both CS and DS Asserted Address Valid and AS Asserted to DS Asserted (Read) CS Asserted to DTACK Low Impedance DS Asserted to DTACK Asserted DS Asserted to AD Low Impedance (Read) DTACK Asserted to Data Valid DS Deasserted to CS Deasserted (Read) DS Deasserted to R/W Invalid DS Deasserted to DTACK Deasserted CS Deasserted to DTACK High Impedance DS Deasserted to Data Invalid (Read) Address Valid and AS Asserted to DS Asserted (Write) Data Valid to DS Asserted DS Deasserted to CS Deasserted (Write) DS Deasserted to Data Valid DS Asserted Width (Write) Address Valid to AS Falling Edge AS Falling Edge to Address Invalid AS Falling Edge to DS Asserted (Read) AS Falling Edge to DS Asserted (Write) CS Asserted to DS Asserted (Write)
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Microprocessor Interface (continued)
Table 67. Microprocessor Interface I/O Timing Specifications (continued) Symbol Configuration Parameter Setup (ns) (Min) -- 10 -- 0 0 -- -- -- -- -- -- -- -- 0 10 10 -- -- -- -- -- 10 -- 0 10 Hold (ns) (Min) 10 -- 10 -- -- -- -- -- -- 5 -- -- 5 -- -- -- 5 -- 10 50 10 -- 10 -- -- Delay (ns) (Max) -- -- -- -- -- 12 15 15 40 -- 15 10 -- -- -- -- -- 15 -- -- -- -- -- -- --
t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55
Modes 3 & 4
ALE Asserted Width Address Valid to ALE Deasserted ALE Deasserted to Address Invalid CS Asserted to RD Asserted Address Valid and ALE Asserted to RD Asserted CS Asserted to RDY Low Impedance Rising Edge MPCK to RDY Asserted RD Asserted to AD Low Impedance RD Asserted to Data Valid RD Deasserted to CS Deasserted RD Deasserted to RDY Deasserted CS Deasserted to RDY High Impedance RD Deasserted to Data Invalid (High Impedance) CS Asserted to WR Asserted Address Valid and ALE Asserted to WR Asserted Data Valid to WR Asserted WR Deasserted to CS Deasserted WR Deasserted to RDY Deasserted WR Deasserted to Data Invalid RD Asserted Width WR Asserted Width Address Valid to ALE Falling Edge ALE Falling Edge to Address Invalid ALE Falling Edge to RD Asserted ALE Falling Edge to WR Asserted
Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 59--Figure 66.
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Microprocessor Interface (continued)
t11 CS t1 AS t2 A[0:11] VALID ADDRESS t12 R/W t5 DS t6 t7 DTACK t9 AD[0:7] t10 VALID DATA
5-6422(F)r.1
t3
t8
t13
t14
t15
Figure 59. Mode 1--Read Cycle Timing (MPMODE = 0, MPMUX = 0)
t18 CS t1 AS t2 A[0:11] VALID ADDRESS t5 R/W t16 t20 DS t25 t7 DTACK t17 AD[0:7] VALID DATA
5-6423(F)
t3
t12
t8
t13
t14
t19
Figure 60. Mode 1--Write Cycle Timing (MPMODE = 0, MPMUX = 0) 130 Lucent Technologies Inc. Lucent Technologies Inc.
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Microprocessor Interface (continued)
t11 CS t1 AS t21 A[8:11] t22
VALID ADDRESS t5 t12
R/W
DS t23 t7 DTACK t21 AD[0:7] t22 t9 t10 VALID DATA t15 t8 t13 t14
VALID ADDRESS
5-6424(F)
Figure 61. Mode 2--Read Cycle Timing (MPMODE = 0, MPMUX = 1)
t18 CS t1 AS t21 A[8:11] t22
VALID ADDRESS t5 t12
R/W t25 DS t24 t7 DTACK t21 AD[0:7] t22 t17 VALID DATA
5-6425(F)
t20
t8
t13
t14
t19
VALID ADDRESS
Figure 62. Mode 2--Write Cycle Timing (MPMODE = 0, MPMUX = 1) Lucent Technologies Inc. Lucent Technologies Inc. 131
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Microprocessor Interface (continued)
t40 CS t31 ALE t32 A[0:11] VALID ADDRESS t34 RD t35 t36 RDY t39 t38 AD[0:7] VALID DATA t43 t37 t41 t42 t50 t33
MPCK
5-6426(F)r.1
Figure 63. Mode 3--Read Cycle Timing (MPMODE = 1, MPMUX = 0)
t47 CS t31 ALE t32 A[0:11] VALID ADDRESS t44 WR t45 t36 RDY t46 AD[0:7] VALID DATA t49 t37 t48 t42 t51 t33
MPCK
5-6427(F)
Figure 64. Mode 3--Write Cycle Timing (MPMODE = 1, MPMUX = 0) 132 Lucent Technologies Inc. Lucent Technologies Inc.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Microprocessor Interface (continued)
t40 CS t31 ALE t52 A[8:11] t53
VALID ADDRESS t34 t50
RD t54 t36 RDY t52 AD t53 t39 t38 t43 VALID DATA t37 t41 t42
VALID ADDRESS
MPCK
5-6428(F)r.1
Figure 65. Mode 4--Read Cycle Timing (MPMODE = 1, MPMUX = 1)
t47 CS t31 ALE t52 A[8:11] t53
VALID ADDRESS t44 t51
WR t55 t36 RDY t52 AD t53 t46 VALID DATA t49 t37 t48 t42
VALID ADDRESS
MPCK
5-6429(F)r.1
Figure 66. Mode 4--Write Cycle Timing (MPMODE = 1, MPMUX = 1) Lucent Technologies Inc. Lucent Technologies Inc. 133
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Reset
Both hardware and software resets are provided.
Software Reset/Software Restart
Independent software reset for each functional block of the device is available. The LIU may be placed in restart through register LIU_REG2 bit 5 (RESTART). The framer may be reset through register FRM_PR26 bit 0 (SWRESET), or placed in restart through FRM_PR26 bit 1 (SWRESTART). The FDL receiver may be reset through register FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through FDL_PR1 bit 5 (FTR). The reset functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver reset), and FTR (FDL transmitter reset), reset the block and return all parameter/control registers for the block to their default values. The restart functions, LIU RESTART and framer SWRESTART (framer software restart), reset the block but do not alter the value of the parameter/control registers.
Hardware Reset (Pin 43/139)
Hardware reset is enabled by asserting RESET to 0. Each channel has independent resets, RESET1 (pin 139) for channel 1 and RESET2 (pin 43) for channel 2. The device is in an inactive condition when RESET is 0, and becomes active when RESET is returned to 1. Eight cycles of the LIU receive line clock, i.e., 5.2 s for T1 or 3.9 s for E1, is required to guarantee a complete reset. Upon completion of a reset cycle, the LIU register default values are controlled by the setting of DS1/CEPT (pin 40/142), as given in Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control. If DS1/CEPT is 1, the defaults are set for DS1 with line equalization for a 1 ft. to 131 ft. span. If DS1/CEPT is 0, the defaults are set for CEPT with a line equalization for 120 twisted pair or 75 coax option 1. Hardware reset of a single channel returns all LIU, framer, and FDL registers of that channel to their default values, as listed in the individual register descriptions and register maps, Table 197--Table 202. Reset of a single channel does not reset the global registers. Hardware reset of both channels simultaneously, both pin 43 and pin 139 set to 0, results in a complete device reset including a reset of the global registers.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Architecture
Table 68 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 68. Register Summary Register Function Register Address (hex) Channel 1 Global Registers GREG0 GREG1 GREG2 GREG3 GREG4 GREG5 GREG6 GREG7 LIU_REG0 LIU_REG1 LIU_REG2 LIU_REG3 LIU_REG4 LIU_REG5 LIU_REG6 Primary Block Interrupt Status Primary Block Interrupt Enable Global Loopback Control Global Loopback Control Global Control Device ID and Version Device ID and Version Device ID and Version LIU Registers LIU Alarm Status LIU Alarm Interrupt Enable LIU Control LIU Control LIU Control LIU Configuration LIU Configuration Framer Registers Status Registers FRM_SR0 FRM_SR1 FRM_SR2 FRM_SR3 FRM_SR4 FRM_SR5 FRM_SR6 FRM_SR7 FRM_SR8, FRM_SR9 FRM_SR10, FRM_SR11 FRM_SR12, FRM_SR13 FRM_SR14, FRM_SR15 Interrupt Status Facility Alarm Condition Remote End Alarm Facility Errored Event Facility Event Exchange Termination and Exchange Termination Remote End Interface Status Network Termination and Network Termination Remote End Interface Status Facility Event Bipolar Violation Counter Framing Bit Error Counter CRC Error Counter E-bit Counter 600 601 602 603 604 605 606 607 608, 609 60A, 60B 60C, 60D 60E, 60F C00 C01 C02 C03 C04 C05 C06 C07 C08, C09 C0A, C0B C0C, C0D C0E, C0F 400 401 402 403 404 405 406 A00 A01 A02 A03 A04 A05 A06 000 001 002 003 004 005 006 007 Channel 2
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Register Architecture (continued)
Table 68. Register Summary (continued) Register Function Register Address (hex) Channel 1 Framer Registers (continued) Status Registers (continued) FRM_SR16, FRM_SR17 FRM_SR18, FRM_SR19 FRM_SR20, FRM_SR21 FRM_SR22, FRM_SR23 FRM_SR24, FRM_SR25 FRM_SR26, FRM_SR27 FRM_SR28, FRM_SR29 FRM_SR30, FRM_SR31 FRM_SR32, FRM_SR33 FRM_SR34, FRM_SR35 FRM_SR36, FRM_SR37 FRM_SR38, FRM_SR39 FRM_SR40, FRM_SR41 FRM_SR42, FRM_SR43 FRM_SR44, FRM_SR45 FRM_SR46, FRM_SR47 FRM_SR48, FRM_SR49 FRM_SR50, FRM_SR51 FRM_SR52 FRM_SR53 FRM_SR54-- FRM_SR63 CRC-4 Error at NT1 from NT2 Counter E-bit at NT1 from NT2 Counter ET Errored Seconds Counter ET Bursty Errored Seconds Counter ET Severely Errored Seconds Counter ET Unavailable Seconds Counter ET-RE Errored Seconds Counter ET-RE Bursty Errored Seconds Counter ET-RE Severely Errored Seconds Counter ET-RE Unavailable Seconds Counter NT1 Errored Seconds Counter NT1 Bursty Errored Seconds Counter NT1 Severely Errored Seconds Counter NT1 Unavailable Seconds Counter NT1-RE Errored Seconds Counter NT1-RE Bursty Errored Seconds Counter NT1-RE Severely Errored Seconds Counter NT1-RE Unavailable Seconds Counter Receive NOT-FAS TS0 Received Sa SLC-96 FDL/CEPT Sa Receive Stack 610, 611 612, 613 614, 615 616, 617 618, 619 61A, 61B 61C, 61D 61E, 61F 620, 621 622, 623 624, 625 626, 627 628, 629 62A, 62B 62C, 62D 62E, 62F 630, 631 632, 633 634 635 636--63F C10, C11 C12, C13 C14, C15 C16, C17 C18, C19 C1A, C1B C1C, C1D C1E, C1F C20, C21 C22, C23 C24, C25 C26, C27 C28, C29 C2A, C2B C2C, C2D C2E, C2F C30, C31 C32, C33 C34 C35 C36--C3F Channel 2
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Architecture (continued)
Table 68. Register Summary (continued) Register Function Framer Registers (continued) Received Signaling Registers FRM_RSR0-- Received Signaling FRM_RSR31 Parameter/Control Registers FRM_PR0-- FRM_PR7 FRM_PR8 FRM_PR9 FRM_PR10 FRM_PR11 FRM_PR12, FRM_PR13 FRM_PR14 FRM_PR15 FRM_PR16 FRM_PR17, FRM_PR18 FRM_PR19 FRM_PR20 FRM_PR21 FRM_PR22 FRM_PR23 FRM_PR24 FRM_PR25 FRM_PR26 FRM_PR27 Interrupt Group Enable Framer Mode Option Framer CRC Control Option Alarm Filter Errored Second Threshold Severely Errored Second Threshold Errored Event Enable ET Remote End Errored Event Enable NT1 Errored Event Enable NT1 Remote End Errored Event Enable 660--667 668 669 66A 66B 66C. 66D 66E 66F 670 671, 672 673 674 675 676 677 678 679 67A 67B 67C 67D 67E 67F--688 689 68A 68B 68C 68D 68E 68F 690 C60--C67 C68 C69 C6A C6B C6C, C6D C6E C6F C70 C71, C72 C73 C74 C75 C76 C77 C78 C79 C7A C7B C7C C7D C7E C7F--C88 C89 C8A C8B C8C C8D C8E C8F C90 640--65F C40--C5F Register Address (hex) Channel 1 Channel 2
Automatic AIS to the System and Automatic Loopback Enable Transmit to the Line Command Framer FDL Loopback Transmission Codes Command Framer Transmit Line Idle Code Framer Transmit System Idle Code Primary Loopback Control Secondary Loopback Control System Frame Sync Mask Source Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A bit = 1 Control FRM_PR28 CEPT Automatic Transmission of E bit = 0 FRM_PR29 Sa4--Sa8 Source FRM_PR30 Sa4--Sa8 Control FRM_PR31-- Sa Transmit Stack/SLC-96 Transmit Stack FRM_PR40 FRM_PR41 Si-bit Source FRM_PR42 Frame Exercise FRM_PR43 System Interface Control FRM_PR44 Signaling Mode FRM_PR45 CHI Common Control FRM_PR46 CHI Common Control FRM_PR47 CHI Transmit Control FRM_PR48 CHI Receive Control
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Register Architecture (continued)
Table 68. Register Summary (continued) Register Function Register Address (hex) Channel 1 Framer Registers (continued) Parameter/Control Registers (continued) FRM_PR49-- FRM_PR52 FRM_PR53-- FRM_PR56 FRM_PR57-- FRM_PR60 FRM_PR61-- FRM_PR64 FRM_PR65 FRM_PR66 FRM_PR69 FRM_PR70 Transmit CHI Time-Slot Enable Receive CHI Time-Sot Enable CHI Transmit Highway Select CHI Receive Highway Select CHI Transmit Control CHI Receive Control Auxiliary Pattern Generator Control Auxiliary Pattern Detector Control 691--694 695--698 699--69C 69D--6A0 6A1 6A2 6A5 6A6 6E0--6F7 Facility Data Link Registers FDL Parameter/Control Registers FDL_PR0 FDL_PR1 FDL_PR2 FDL_PR3 FDL_PR4 FDL_PR5 FDL_PR6 FDL_PR7 FDL_PR8 FDL_PR9 FDL_PR10 FDL_SR0 FDL_SR1 FDL_SR2 FDL_SR3 FDL_SR4 FDL Configuration Control FDL Control FDL Interrupt Mask Control FDL Transmitter Configuration Control FDL Transmitter FIFO FDL Transmitter Mask FDL Receive Interrupt Level Control Not Assigned FDL Receive Match Character FDL Transparent Control FDL Transmit ANSI ESF Bit Codes FDL Interrupt Status FDL Transmitter Status FDL Receiver Status FDL ANSI Bit Codes Status FDL Receive FIFO 800 801 802 803 804 805 806 -- 808 809 80A 80B 80C 80D 80E 807 E00 E01 E02 E03 E04 E05 E06 -- E08 E09 E0A E0B E0C E0D E0E E07 C91--C94 C95--C98 C99--C9C C9D--CA0 CA1 CA2 CA5 CA6 CE0--CF7 Channel 2
Transmit Signaling Registers FRM_TSR0-- Transmit Signaling FRM_TSR31
FDL Status Registers
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Global Register Architecture
REGBANK0 contains the status and programmable control registers for all global functions. The address of these registers is 000 (hex) to 007 (hex). These registers control both channels of the terminator. The register bank architecture is shown in Table 69. The register bank consists of 8-bit registers classified as primary block interrupt status register, primary block interrupt enable register, global loopback control register, global terminal control register, device identification register, and global internal interface control register. GREG0 is a clear on read (COR) register. This register is cleared by the framer internal received line clock (LIU_RLCK of Figure 18 Block Diagram of Framer Line Interface on page 46). At least two RFRMCK cycles (1.3 s for DS1 and 1.0 s for CEPT) must be allowed between successive reads of the same COR register to allow it to properly clear. The default values are shown in parentheses. Table 69. Global Register Set (0x000--0x008)
Global Register [Address (hex)]
GREG0[000] GREG1[001] GREG2[002] GREG3[003] GREG4[004] GREG5[005] GREG6[006] GREG7[007]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved FDL2INT FRMR2INT LIU2INT Reserved FDL1INT FRMR1INT LIU1INT (0) (0) (0) (0) (0) (0) (0) (0) Reserved FDL2IE FRMR2IE LIU2IE Reserved FDL1IE FRMR1IE LIU1IE (0) (0) (0) (0) (0) (0) (0) (0) TID2-RSD1 TSD2-RSD1 TID1-RSD1 TSD1-RSD1 TSD2-RID1 TID2-RID1 TSD1-RID1 TID1-RID1 (0) (0) (0) (0) (0) (0) (0) (0) TID1-RSD2 TSD1-RSD2 TID2-RSD2 TSD2-RSD2 TSD1-RID2 TID1-RID2 TSD2-RID2 TID2-RID2 (0) (0) (0) (0) (0) (0) (0) (0) Reserved ALIE SECCTRL Reserved T1-R2 T2-R1 Reserved Reserved (0) (0) (0) (0) (0) (0) (0) (0) 0 1 1 1 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0
The following section describes the global registers in Tables 70--75.
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Global Register Structure
Primary Block Interrupt Status Register (GREG0)
A bit set to 1 indicates the block has recently generated an interrupt. This register is cleared on read. Table 70. Primary Block Interrupt Status Register (GREG0) (000) Bit 0 1 2 3 4 5 6 7 Symbol LIU1INT FRMR1INT FDL1INT -- LIU2INT FRMR2INT FDL2INT -- Description Line Interface Unit 1 Interrupt. A 1 indicates LIU1 generated an interrupt. Framer 1 Interrupt. A 1 indicates framer 1 generated an interrupt. Facility Data Link 1 Interrupt. A 1 indicates FDL1 generated an interrupt. Reserved. Line Interface Unit 2 Interrupt. A 1 indicates LIU2 generated an interrupt. Framer 2 Interrupt. A 1 indicates framer 2 generated an interrupt. Facility Data Link 2 Interrupt. A 1 indicates FDL2 generated an interrupt. Reserved.
Primary Block Interrupt Enable Register (GREG1)
This register enables the individual blocks to assert the interrupt pin. Table 71. Primary Block Interrupt Enable Register (GREG1) (001) Bit 0 1 2 3 4 5 6 7 Symbol LIU1IE FRMR1IE FDL1IE -- LIU2IE FRMR2IE FDL2IE -- Description Line Interface 1 Interrupt Enable. A 1 enables LIU1 interrupts. Framer 1 Interrupt Enable. A 1 enables framer 1 interrupts. Facility Data Link 1 Interrupt Enable. A 1 enables FDL1 interrupts. Reserved. Write to 0. Line Interface 2 Interrupt Enable. A 1 enables LIU2 interrupts. Framer 2 Interrupt Enable. A 1 enables framer 2 interrupts. Facility Data Link 2 Interrupt Enable. A 1 enables FDL2 interrupts. Reserved. Write to 0.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Global Register Structure (continued)
Global Loopback Control Register (GREG2)
This register enables the framer inputs RCHIDATA1 and RCHIDATAB1 to be driven by various internal sources. A 1 enables the specified loopback. The default of the register 00 (hex) disables all loopbacks and enables external sources to drive these inputs. Table 72. Global Loopback Control Register (GREG2) (002) Bit 0 1 2 3 4 5 6 7 Symbol TID1--RID1 TSD1--RID1 TID2--RID1 TSD2--RID1 TSD1--RSD1 TID1--RSD1 TSD2--RSD1 TID2--RSD1 Description TCHIDATA1 to RCHIDATA1 Connection. TCHIDATAB1 to RCHIDATA1 Connection. TCHIDATA2 to RCHIDATA1 Connection. TCHIDATAB2 to RCHIDATA1 Connection. TCHIDATAB1 to RCHIDATAB1 Connection. TCHIDATA1 to RCHIDATAB1 Connection. TCHIDATAB2 to RCHIDATAB1 Connection. TCHIDATA2 to RCHIDATAB1 Connection.
Global Loopback Control Register (GREG3)
This register enables the framer inputs RCHIDATA2 and RCHIDATAB2 to be driven by various internal sources. A 1 enables the specified loopback. The default of the register 00 (hex) disables all loopbacks and enables external sources to drive these inputs. Table 73. Global Loopback Control Register (GREG3) (003) Bit 0 1 2 3 4 5 6 7 Symbol TID2--RID2 TSD2--RID2 TID1--RID2 TSD1--RID2 TSD2--RSD2 TID2--RSD2 TSD1--RSD2 TID1--RSD2 Description TCHIDATA2 to RCHIDATA2 Connection. TCHIDATAB2 to RCHIDATA2 Connection. TCHIDATA1 to RCHIDATA2 Connection. TCHIDATAB1 to RCHIDATA2 Connection. TCHIDATAB2 to RCHIDATAB2 Connection. TCHIDATA2 to RCHIDATAB2 Connection. TCHIDATAB1 to RCHIDATAB2 Connection. TCHIDATA1 to RCHIDATAB2 Connection.
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Global Register Structure (continued)
Global Control Register (GREG4)
This register enables LIU1 to LIU2 loopbacks (bit 2 and bit 3), source of the output second pulse (bit 5), interrupt polarity (bit 6), and source of framer resets (bit 7). Table 74. Global Control Register (GREG4) (004) Bit 0 1 2 3 4 5 6 7 Symbol -- -- T2-R1 T1-R2 -- SECCTRL ALIE -- Description Reserved. Write to zero. Reserved. Write to zero. TLCK2, TPD2, and TND2 to RLCK1, RPD1, and RND1 Connection. A 1 makes the indicated loopback. TLCK1, TPD1, and TND1 to RLCK2, RPD2, and RND2 Connection. A 1 makes the indicated loopback. Reserved. Write to zero. SECOND Pulse Source Control. A 0 enables framer 1 to source the output second pulse (SECOND). A 1 enables framer 2 to source the output second pulse. Active-Low Interrupt Enable. A 1 enables active-low interrupt. Reserved. Write to zero.
Device ID and Version Registers (GREG5--GREG7)
These bits define the device and version number. Table 75. Device ID and Version Registers (GREG5--GREG7) (005--007) Register Device Code Device Code Version # GREG5 GREG6 GREG7 Bit 7 0 0 0 Bit 6 1 0 0 Bit 5 1 1 0 Bit 4 1 1 0 Bit 3 0 0 0 Bit 2 1 0 0 Bit 1 1 0 1 Bit 0 0 0 0
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Unit (LIU) Register Architecture
REGBANK2 and REGBANK5 contain the status and programmable registers for the line interface unit channels LIU1 and LIU2 respectively. The base address for REGBANK2 is 400(hex) and for REGBANK5 is A00(hex). Within these register banks, the bit map is identical for both LIU1 and LIU2. The register bank architecture for LIU1 and LIU2 is shown in Table 76. The register bank consists of 8-bit registers classified as alarm status register, alarm mask register, status register, status interrupt mask register, control registers, and configuration registers. Register LIU_REG0 is the alarm status register used for storing the various LIU alarms and status. It is a read-only, clear-on-read (COR) register. This register is cleared on the rising edge of MPCLK, if present, or on the rising edge of the internally generated 2.048 MHz clock derived from the CHI clock if MPCLK is not present. Register LIU_REG1 contains the individual interrupt enable bits for the alarms in LIU_REG0. Register LIU_REG2, LIU_REG3, and LIU_REG4 are designated as control registers while LIU_REG5 and LIU_REG6 are configuration registers. These are used to set up the individual LIU channel functions and parameters. The default values are shown in parentheses. The following sections describe the LIU registers in more detail. Table 76. Line Interface Units Register Set* ((400--40F); (A00--A0F))
LIU Register LIU Register [Address (HEX)] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Alarm Register (Read Only) (Latches Alarm, Clear On Read)
LIU_REG0 400; A00 0 0 0 0 LOTC TDM DLOS ALOS
Alarm Interrupt Enable Register (Read/Write)
LIU_REG1 401; A01 Reserved (0) Reserved (0) Reserved (0) Reserved (0) LOTCIE (0) TDMIE (0) DLOSIE (0) ALOSIE (0)
Control Registers (Read/Write)
LIU_REG2 LIU_REG3 LIU_REG4 402; A02 403; A03 404; A04 Reserved (0) Reserved (1) Reserved (0) Reserved (0) Reserved (1) Reserved (0) RESTART (0) Reserved (1) JABW0 (0) HIGHZ (0) LOSSD (0) PHIZALM (0) Reserved (0) DUAL (0) PRLALM (0) LOSST (0) CODE (1) PFLALM (0)
Reserved Reserved (0) (0)
JAT (0) RCVAIS (0)
JAR (0) ALTIMER (0)
Configuration Registers (Read/Write)
LIU_REG5 LIU_REG6 405; A05 406; A06 Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) LOOPA (0) Reserved LOOPB XLAIS (0) (1) EQ2 EQ1 (0,DS1) (0,DS1) (1,CEPT) (1,CEPT) PWRDN (0) EQ0 (0)
0(0)
* The logic value, in parentheses below each bit definition, is the default state upon completion of hardware reset. These bits must be written to 1.
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Line Interface Alarm Register
Alarm Status Register (LIU_REG0)
Bits 0--3 of this register represent the status of the line interface receiver and transmitter alarms ALOS, DLOS, TDM, and LOTC. The alarm indicators are active-high and automatically clear on a microprocessor read if the corresponding alarm conditions no longer exist.* However, persistent alarm conditions will cause these bits to remain set even after a microprocessor read. This is a read-only register. Table 77. LIU Alarm Status Register (LIU_REG0) (400, A00) Bit 0 1 2 3 4--7 Symbol ALOS DLOS TDM LOTC -- Description Receive Analog Loss of Signal. A 1 indicates the LIU receive channel has detected an analog loss of signal condition/event. Receive Digital Loss of Signal. A 1 indicates the LIU receive channel has detected a digital loss of signal condition/event. Transmit Driver Monitor Alarm. A 1 indicates the LIU transmit channel has detected a transmit driver monitor alarm condition/event. Transmit Loss of Transmit Clock Alarm. A 1 indicates the LIU transmit channel has detected a loss of transmit clock condition/event. Reserved.
Line Interface Alarm Interrupt Enable Register
Alarm Interrupt Enable Register (LIU_REG1)
The bits in the alarm interrupt enable register allow the user to selectively enable generation of an interrupt by each channel alarm. The enable bits correspond to their associated alarm status bits in the alarm status register, LIUREG0. The interrupt enable function is active-high. When an enable bit is set, the corresponding alarm is enabled to generate an interrupt. Otherwise, the alarm is disabled from generating an interrupt. The enable function only impacts the ability to generate an interrupt signal. The proper alarm status will be reflected in LIU_REG0 even when the corresponding enable bit is set to zero. Any other LIU behavior associated with an alarm event will operate normally even if the interrupt is not enabled. This is a read/write register Table 78. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01) Bit 0 1 2 3 4--7 Symbol ALOSIE DLOSIE TDMIE LOTCIE -- Description Enable Analog Loss of Signal Interrupt. A 1 enables an interrupt in response to ALOS alarm. Enable Digital Loss of Signal Interrupt. A 1 enables an interrupt in response to DLOS alarm. Enable Transmit Driver Monitor Interrupt. A 1 enables an interrupt in response to TDM alarm. Enable loss of Transmit Clock Interrupt. A 1 enables an interrupt in response to LOTC alarm. Reserved. Write to 0.
* See T7630 Device Advisory for signal timing requirements.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Line Interface Control Registers
The bits in the control registers allow the user to configure the various device functions for the individual line interface channels 1 and 2. All the control bits (with the exception of LOSSTD) are active-high.
LIU Control Register (LIU_REG2)
Table 79. LIU Control Register (LIU_REG2) (402, A02) Bit 0 1 2 Symbol -- -- LOSSTD Description Reserved. Write to 0. Reserved. Write to 0. The LOSSTD bit selects the conformance protocol for the DLOS receiver alarm function. LOSSTD = 0 selects standards T1M1.3/93-005, ITU-T G.755 for DS1 mode and ITU-T G.755 for CEPT mode. LOSSTD = 1 selects standards TR-TSY000009 for DS1 and ITU-T G.775 for CEPT. Reserved. Write to 0. The HIGHZ bit places the LIU in a high-impedance state. When HIGHZ = 1, the TTIP and TRING transmit drivers for the specified channel are placed in a highimpedance state. The RESTART bit is used for device initialization through the microprocessor interface. RESTART = 1 resets the data path circuits. Data path circuits will be reset, but the microprocessor registers state will not be altered by a restart action. Reserved. Write to 0.
3 4
-- HIGHZ
5
RESTART
6--7
--
LIU Control Register (LIU_REG3)
The default value of this register is E4 (hex) Table 80. LIU Control Register (LIU_REG3) (403, A03). Bit 0 Symbol JAR Description The JAR bit is used to enable and disable the jitter attenuator function in the receive path. The JAR and JAT control bits are mutually exclusive, i.e., either JAR or the JAT control bit can be set, but not both. JAR = 1 places jitter attenuator in the receive path. The JAT bit is used to enable and disable the jitter attenuator function in the transmit path. The JAT and JAR control bits are mutually exclusive, i.e., either JAT or the JAR control bit can be set, but not both. JAT = 1 places jitter attenuator in the transmit path. The CODE bit is used to enable and disable the B8ZS/HDB3 zero substitution coding in the transmit and decoding in the receive path. CODE is used in conjunction with the DUAL bit and is valid only for single-rail operation. CODE = 1 activates the coding/ decoding functions. The default value is CODE = 1. The DUAL bit is used to select single- or dual-rail mode of operation. DUAL = 1 selects the dual-rail mode. The LOSSD bit selects the shutdown function for the receiver during DLOS. LOSSD operates in conjunction with the RCVAIS bit (see Table 4, LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes), repeated below for reference) Reserved. Write to 1.
1
JAT
2
CODE
3 4
DUAL LOSSD
5--7
--
Note: These registers must be written to 1 for the LIU-to-framer interface to be functional.
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Line Interface Control Registers (continued)
Table 81. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 4) LOSSD 0 0 1 1 0 0 1 1 RCVAIS 0 0 0 0 1 1 1 1 ALARM ALOS DLOS ALOS DLOS ALOS DLOS ALOS DLOS RPD/RND 0 Normal Data 0 0 AIS (all ones) AIS (all ones) 0 0 RLCK Free Runs Recovered Clock Free Runs Free Runs Free Runs Free Runs Free Runs Free Runs
LIU Control Register (LIU_REG4)
Table 82. LIU Register (LIU_REG4) (404, A04) Bit 0 1 Symbol ALTIMER RCVAIS Description The ALTIMER bit is used to select the time required to declare ALOS. ALTIMER = 0 selects 1 ms--2.6 ms. ALTIMER = 1 selects 10 bit to 255 bit periods. The RCVAIS bit selects the shut down function for the receiver during ALOS alarm (ALOS). RCVAIS operates in conjunction with the LOSSD bit. See LIU-REG3. PFLALM prevents the DLOS alarm from occurring during FLLOOP activation. PFLALM = 1 activates the PFLALM function. PRLALM prevents the LOTC alarm from occurring during RLOOP activation/deactivation. PRLALM = 1 activates the PRLALM function. PHIZALM prevents the TDM alarm from occurring when the driver are in a highimpedance state. PHIZALM = 1 activates the PHIZALM function. JABW0 = 1 selects the lower bandwidth jitter attenuator option in CEPT mode.
2 3 4 5
PFLALM PRLALM PHIZALM JABW0
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Line Interface Control Registers (continued)
LIU Configuration Register (LIU_REG5)
The control bits in the channel configuration register 5 are used to select powerdown mode, AIS generation, and loopbacks for the LIU. The PWRDN and XLAIS bits are active-high. This is a read/write register. The default value of this register is 02 (hex). Table 83. LIU Configuration Register (LIU_REG5) (405, A05) Bit 0 1 Symbol PWRDN XLAIS Description PWRDN = 1 activates powerdown. XLAIS = 1 enables transmission of an all ones signal to the line interface. XLAIS = 1 after a reset allowing immediate generation of alarm signal as long as a clock source is present. The default value is XLAIS = 1. The LOOPA bit is used in conjunction with LOOPB to select the channel loopback modes. See Table 11, repeated below for reference. Reserved. Write to 0.
2 3 4--7
LOOPB LOOPA --
Table 84. Loopback Control (from Table 11) Operation Normal* Full Local Loopback Remote Loopback Digital Local Loopback Symbol -- FLLOOP RLOOP DLLOOP LOOPA 0 0 1 1 LOOPB 0 1 0 1
* The reset default condition is LOOPA = LOOPB = 0 (no loopback). During the transmit AIS condition, the looped data will be the transmitted data from the framer or system interface and not the all ones signal. Transmit AIS request is ignored.
LIU Configuration Register (LIU_REG6)
The control bits in the channel configuration register 6 are used to select LIU transmit equalization settings. This is a read/write register. The default value of this register is 00 (hex) in DS1 when DS1/CEPT (pin 40/142) is set to 1, and 06 (hex) in CEPT when DS1/CEPT (pin 40/142) is set to 0. Table 85. LIU Configuration Register (LIU_REG6) (406, A06) Bit 0 1 2 3--7 Symbol EQ0 EQ1 EQ2 -- Description The EQ0, EQ1, and EQ2 bits select the type of service (DS1 or CEPT) and the associated transmitter cable equalization/line build out/termination impedances. See Table 7, Transmit Line Interface Short-Haul Equalizer/Rate Control, repeated below for reference. Reserved. Write to 0.
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Line Interface Control Registers (continued)
Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 7) Short-Haul Applications EQ2 EQ1 EQ0 Service Clock Rate Transmitter Equalization* Maximum Cable Loss to DSX dB 0.6 1.2 1.8 2.4 3.0 --
Feet 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DSX-1 1.544 MHz
Meters
CEPT
2.048 MHz
0 to 131 0 to 40 131 to 262 40 to 80 262 to 393 80 to 120 393 to 524 120 to 160 524 to 655 160 to 200 75 (Option 2) 120 or 75 (Option 1) Not Used
* In DS1 mode, the distance to the DSX for 22-Gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types. In CEPT mode, equalization is specified for coaxial or twisted-pair cable. Reset default state is EQ2, EQ1, and EQ0 = 000 when pin DS1_CEPT = 1 and EQ2, EQ1, and EQ0 = 110 when pin DS1_CEPT = 0. Loss measured at 772 kHz. In 75 applications, Option 1 is recommended over Option 2 for lower LIU power dissipation. Option 2 allows for the use of the same transformer as in CEPT 120 applications (see Line Interface Unit: Line Circuitry section).
Framer Register Architecture
REGBANK3 and REGBANK6 contain the status and programmable control registers for the framer and system (CHI) interface channels FRM1 and FRM2. The base address for REGBANK3 is 600 (hex) and for REGBANK6 is C00 (hex). Within these register banks, the bit map is identical for both FRM1 and FRM2. The framer registers are structures as shown in Table 87. Default values are given in the individual register definition tables. Table 87. Framer Status and Control Blocks Address Range (Hexadecimal) Framer Register Block Status Registers (COR) ((600--63F); (C00--C3F)) Receive Signaling Registers ((640--65F); (C40--C5F)) Parameter (Configuration) Registers ((660--6A6); (C60--CA6)) Transmit Signaling Registers ((6E0--6FF); (CE0--CFF)) The complete register map for the framer is given in Table 201 to Table 203. All status registers are clocked with the internal framer receive line clock (RFRMCK). Bits in status registers FRM_SR1 and FRM_SR7 are set at the onset of the condition and are cleared on read when the given condition is no longer present. These registers can generate interrupts if the corresponding register bits are enabled in interrupt enable registers FRM_PR0--FRM_PR7.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
On all 16-bit counter registers (FRM_SR8--FRM_SR51), both bytes are cleared only after reading both bytes. These status registers are two byte register pairs. These register pairs must be read in succession, with the lower byte read first followed by a read of higher byte. Once a read is initiated on one of the bytes, the updating of that counter is disabled and remains disabled until both bytes are read. All events during this interval are lost. Updating of the counter registers is stopped when all of the bits are set to 1. Updating resumes after the registers are cleared on read. These register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be followed immediately by a read of the remaining byte of the pair. Status registers FRM_SR0--FRM_SR63 are clear-on-read (COR) registers. These registers are cleared by the framer internal received line clock (RFRMCK). At least two RFRMCK cycles (1.3 s for DS1 and 1.0 s for CEPT) must be allowed between successive reads of the same COR register to allow it to properly clear.
Framer Status/Counter Registers
Registers FRM_SR0--FRM_SR63 report the status of each framer. All are clear-on-read, read only registers. Interrupt Status Register (FRM_SR0) The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in registers FRM_PR0--FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1. Table 88. Interrupt Status Register (FRM_SR0) (600; C00) Bit 0 1 2 3 4 5 6 7 Symbol FAC RAC FAE ESE TSSFE RSSFE -- S96SR Description Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1). Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2). Facility Alarm Event. A 1 indicates a facility alarm occurred (go read FRM_SR3 and FRM_SR4). Errored Second Event. A 1 indicates an errored second event occurred (go read FRM_SR5, FRM_SR6, and FRM_SR7). Transmit Signaling Superframe Event. A 1 indicates that a MOS superframe block has been transmitted and the transmit signaling data buffers are ready for new data. Receive Signaling Superframe Event. A 1 indicates that a MOS superframe block has been received and the receive signaling data buffers must be read. Reserved. SLC-96 Stack Ready. A 1 indicates that either the transmit framer SLC-96 stack is ready for more data or the receive framer SLC-96 stack contains new data.
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Framer Register Architecture (continued)
Facility Alarm Condition Register (FRM_SR1) The bits in the facility alarm condition register (FRM_SR1) indicate alarm state of the receive framer section. Interrupts from this register are generated once at the onset of the alarm condition. If the alarm condition is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. If the alarm condition is no longer present at the time of the read, then the bit is cleared on read. Table 89. Facility Alarm Condition Register (FRM_SR1) (601; C01) Bit 0 1 Symbol LFA LSFA Description Loss of Frame Alignment. A 1 indicates the receive framer is in a loss of frame alignment and is currently searching for a new alignment. Loss of Signaling Superframe Alignment. A 1 indicates the receive framer is in a loss of signaling superframe alignment in the DS1 framing formats. A search for a new signaling superframe alignment starts once frame alignment is established. Loss of Time Slot 16 Signaling Multiframe Alignment. A 1 indicates the receive framer is in a loss of time slot 16 signaling multiframe alignment in the CEPT mode. A search for a new time slot 16 signaling multiframe alignment starts once frame alignment is established. This bit is 0 when the T7630 is programmed for the transparent signaling mode, register FRM_PR44 bit 0 (TSIG) = 1. Loss of Transmit Superframe Alignment. A 1 indicates superframe alignment pattern in the transmit facility data link as defined for SLC-96 is lost. Only valid for SLC-96 mode. This bit is 0 in all other DS1 modes. Loss of Time Slot 0 CRC-4 Multiframe Alignment. A 1 indicates an absence of CRC4 multiframe alignment after initial basic frame alignment is established. A 0 indicates either CRC-4 checking is disabled or CRC-4 multiframe alignment has been successfully detected. Loss of Frame Alignment Since Last Read. A 1 indicates that the LFA state indicated in bit 0 of this register is the same LFA state as the previous read. Loss of Biframe Alignment. A 1 indicates that the CEPT biframe alignment pattern (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. This alignment pattern is required when transmitting the Si or Sa bits transparently. Only valid in the CEPT mode. This bit is 0 in all other modes. Receive Time Slot 16 Alarm Indication Signal. A 1 indicates the receive framer detected time slot 16 AIS in the CEPT mode. This bit is 0 in the DS1 modes. Auxiliary Pattern. A 1 indicates the detection of a valid AUXP (unframed 1010 . . . pattern) in the CEPT mode. This bit is 0 in the DS1 modes. Alarm Indication Signal. A 1 indicates the receive framer is currently receiving an AIS pattern from its remote line end.
LTS16MFA
2
LTSFA
LTS0MFA
3 4
LFALR LBFA
5 6 7
RTS16AIS AUXP AIS
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Remote End Alarm Register (FRM_SR2) A bit set to 1 indicates the receive framer has recently received the given alarm. Interrupts from this register are generated once at the beginning of the alarm condition. If the alarm is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. If the alarm condition is no longer present at the time of the read, then the bit is cleared on read. Table 90. Remote End Alarm Register (FRM_SR2) (602; C02) Bit 0 1 Symbol RFA RJYA RTS16MFA 2 3 4 5 6 7 CREBIT Sa6 = 8 Sa6 = A Sa6 = C Sa6 = E Sa6 = F Description Remote Framer Alarm. A 1 indicates the receive framer detected a remote frame (yellow) alarm. Remote Japanese Yellow Alarm. A 1 indicates the receive framer detected the Japanese format remote frame alarm. Remote Multiframe Alarm. A 1 indicates the receive framer detected a time slot 16 remote frame alarm in the CEPT mode. Continuous Received E Bits. A 1 indicates the detection of a five-second interval containing 991 E bit = 0 events in each second. This bit is 0 in the DS1 mode. Received Sa6 = 8. A 1 indicates the receive framer detected a Sa6 code equal to 1000. This bit is 0 in the DS1 mode. Received Sa6 = A. A 1 indicates the receive framer detected a Sa6 code equal to 1010. This bit is 0 in the DS1 mode. Received Sa6 = C. A 1 indicates the receive framer detected a Sa6 code equal to 1100. This bit is 0 in the DS1 mode. Received Sa6 = E. A 1 indicates the receive framer detected a Sa6 code equal to 1110. This bit is 0 in the DS1 mode. Received Sa6 = F. A 1 indicates the receive framer detected a Sa6 code equal to 1111. This bit is 0 in the DS1 mode.
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Framer Register Architecture (continued)
Facility Errored Event Register (FRM_SR3) A bit set to 1 indicates the receive framer has recently received the given errored event. Table 91. Facility Errored Event Register-1 (FRM_SR3) (603; C03) Bit 0 1 2 3 Symbol LFV FBE CRCE ECE Description Line Format Violation. A 1 indicates the receive framer detected a bipolar line coding or excessive zeros violation. Frame-Bit Errored. A 1 indicates the receive framer detected a frame-bit or frame alignment pattern error. CRC Errored. A 1 indicates the receive framer detected CRC errors. Excessive CRC Errors. A 1 indicates the receive framer detected an excessive CRC errored condition. This bit is only valid in the ESF and CEPT with CRC-4 modes; otherwise, it is 0. Received E Bit = 0. A 1 indicates the receive framer detected a E bit = 0 in either frame 13 or 15 of the time slot 0 of CRC-4 multiframe. This bit is 0 in the DS1 modes. Lack of CRC-4 Multiframe Alignment Timer Expire Indication. A 1 indicates that either the 100 ms or the 400 ms CRC-4 interworking timer expired. Active only immediately after establishment of the initial basic frame alignment. This bit is 0 in the DS1 modes. Receive Elastic Store Slip: Buffer Overflow. A 1 indicates the receive elastic store performed a control slip due to an elastic buffer overflow condition. Receive Elastic Store Slip: Buffer Underflow. A 1 indicates the receive elastic store performed a control slip due to an elastic buffer underflow condition.
4 5
REBIT LCRCATMX
6 7
SLIPO SLIPU
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Framer Register Architecture (continued)
Table 92. Facility Event Register-2 (FRM_SR4) (604; C04) Bit 0 1 Symbol NFA Description
2
3
4
5
6
7
New Frame Alignment. A 1 indicates the receive framer established a new frame alignment which differs from the previous alignment. Signaling Superframe Alignment. A 1 indicates the receive framer has established the SSFA signaling superframe alignment. In the SF modes (D4 and SLC-96) and CEPT modes, this alignment is established only after primary frame alignment is determined. T1 Line Loopback Off Code Detect. A 1 indicates the receive framer detected the DS1 LLBOFF line loopback disable code in the payload. This code is defined in AT&T Technical Reference 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. New Biframe Alignment Established. A 1 indicates the transmit framer has established BFA a biframe alignment for the transmission of transparent Si and or Sa bits from the system data in the CEPT mode. T1 Line Loopback On Code Detect. A 1 indicates the receive framer detected the line LLBON loopback enable code in the payload. This code is defined in AT&T Technical Reference 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. New CEPT CRC-4 Multiframe Alignment. A 1 indicates the CEPT CRC-4 multiframe CMA alignment in the receive framer has been established. FDL-PLBON ESF FDL Payload Loopback On Code Detect. A 1 indicates the receive framer detected the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the MSB. SLC-96 Receive FDL Stack Ready. A 1 indicates that the receive FDL stack should be SLCRFSR read. This bit is cleared on read. Data in the receive FIFO must be read within 9 ms of this interrupt. This bit is not updated during loss of frame or signaling superframe alignment. FDL-PLBOF ESF FDL Payload Loopback Off Code Detect. A 1 indicates the receive framer detected the line loopback disable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost bit is the MSB. SLC-96 Transmit FDL Stack Ready. A 1 indicates that the transmit FDL stack is ready SLCTFSR for new data. This bit is cleared on read. Data written within 9 ms of this interrupt will be transmitted in the next SLC-96 D-bit superframe interval. FDL-LLBON ESF FDL Line Loopback On Code Detect. A 1 indicates the receive framer detected the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111101110000 pattern in the facility data link, where the leftmost bit is the MSB. CEPT Receive Sa Stack Ready. A 1 indicates that the receive Sa6 stack should be RSaSR read. This bit is clear on the first access to the Sa receive stack or at the beginning of frame 0 of the CRC-4 double-multiframe. Data in the receive FIFO must be read within 4 ms of this interrupt. This bit is not updated during LFA. FDL-LLBOFF ESF FDL Line Loopback Off Code Detect. A 1 indicates the receive framer detected the line loopback disable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111100011100 pattern in the facility data link, where the leftmost bit is the MSB. CEPT Transmit Sa Stack Ready. A 1 indicates that the transmit Sa stack is ready for TSaSR new data. This bit is cleared on the first access to the Sa transmit stack or at the beginning of frame 0 of the CRC-4 double multiframe. Data written within 4 ms of this interrupt will be transmitted in the next CRC-4 double multiframe interval. 153
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Framer Register Architecture (continued)
The following registers are dedicated to the exchange termination and its remote end interface. The alarm conditions to trigger errored seconds and severely errored seconds are defined in Table 44, Event Counters Definition and the ET and ET-RE enable registers, FRM_PR14 and FRM_PR15. The thresholds are defined in registers FRM_PR11--FRM_PR13. Table 93. Exchange Termination and Exchange Termination Remote End Interface Status Register (FRM_SR5) (605; C05) Bit 0 1 2 3 Symbol ETES ETBES ETSES ETUAS Description ET Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination (ET). ET Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET. ET Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the ET. ET Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition. ET-RE Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination remote end (ET-RE). ET-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET-RE. ET-RE Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the ET-RE. ET-RE Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition.
4 5 6 7
ETREES ETREBES ETRESES ETREUAS
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Framer Register Architecture (continued)
The following status registers are dedicated to the NT1 and the NT1 remote end (NT1-RE) interface. The alarm conditions to evaluate errored seconds and severely errored seconds are defined in Table 44, Event Counters Definition and the NT1 and NT1-RE enable registers, FRM_PR16--FRM_PR18. The thresholds are defined in registers FRM_PR11--FRM_PR13. Table 94. Network Termination and Network Termination Remote End Interface Status Register (FRM_SR6) (606; C06) Bit 0 1 2 3 Symbol NTES NTBES NTSES NTUAS Description NT Errored Second. A 1 indicates the receive framer detected an errored second at the network termination (NT). NT Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the NT. NT Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the NT. NT Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition. NT-RE Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination remote end (ET-RE). NT-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET-RE. NT-RE Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the NT-RE. NT-RE Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition.
4 5 6 7
NTREES NTREBES NTRESES NTREUAS
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Framer Register Architecture (continued)
Bit 0--bit 4 in this register are set high when the receive framer comes out of the unavailable state, while bit 4-- bit 7 report detection of the receive test patterns. Bits 4 and 5 are cleared only after register FRM_PR70 bit 2 is set to 0. Table 95. Facility Event Register (FRM_SR7) (607; C07) Bit 0 1 2 3 4 5 6 7 Symbol OUAS EROUAS NT1OUAS NROUAS DETECT PTRNBER RPSUEDO RQUASI Description Out of Unavailable State. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the ET. Out of Unavailable State at the ET-RE. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the ET-RE. Out of Unavailable State at the NT1. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the NT. Out of Unavailable State NT1-RE. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the NT-RE. Test Pattern Detected. A 1 indicates the pattern detector has locked onto the pattern specified by the PTRN configuration bits defined in register FRM_PR70. Test Pattern Bit Error. A 1 indicates the pattern detector has found one or more single bit errors in the pattern that it is currently locked onto. Receiving Pseudorandom Pattern. A 1 indicates the receive framer pattern monitor circuit is currently detecting the 215 - 1 pseudorandom pattern*. Receiving Quasi-Random Pattern. A 1 indicates the receive framer pattern monitor circuit is currently detecting the 220 - 1 quasi-random pattern*.
* It is possible for one of these bits to be set to 1, if the received line data is all zeros.
Bipolar Violation Counter Register (FRM_SR8--FRM_SR9) This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. Table 96. Bipolar Violation Counter Registers (FRM_SR8--FRM_SR9) ((608--609); (C08--C09)) Register FRM_SR8 FRM_SR9 Byte MSB LSB Bit 7--0 7--0 Symbol BPV15--BPV8 BPV7--BPV0 BPVs Counter. BPVs Counter. Description
Frame Bit Errored Counter Register (FRM_SR10--FRM_SR11) This register contains the 16-bit count of framing bit errors. Framing bit errors are not counted during loss of frame alignment. Table 97. Framing Bit Error Counter Registers (FRM_SR10--FRM_SR11) ((60A--60B); (C0A--C0B)) Register FRM_SR10 FRM_SR11 Byte MSB LSB Bit 7--0 7--0 Symbol FBE15--FBE8 FBE7--FBE0 Description Frame Bit Errored Counter. Frame Bit Errored Counter.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
CRC Error Counter Register (FRM_SR12--FRM_SR13) This register contains the 16-bit count of CRC errors. CRC errors are not counted during loss of CRC multiframe alignment. Table 98. CRC Error Counter Registers (FRM_SR12--FRM_SR13) ((60C--60D); (C0C--C0D)) Register FRM_SR12 FRM_SR13 Byte MSB LSB Bit 7--0 7--0 Symbol CEC15--CEC8 CEC7--CEC0 CRC Errored Counter. CRC Errored Counter. Description
E-Bit Counter Register (FRM_SR14--FRM_SR15) This register contains the 16-bit count of received E bit = 0 events. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 99. E-Bit Counter Registers (FRM_SR14--FRM_SR15) ((60E--60F); (C0E--C0F)) Register FRM_SR14 FRM_SR15 Byte MSB LSB Bit 7--0 7--0 Symbol REC15--REC8 REC7--REC0 E-Bit Counter. E-Bit Counter. Description
CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) This register contains the 16-bit count of each occurrence of Sa6 code 001X, detected synchronously to the CEPT CRC-4 multiframe. Table 100. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) ((610--611); (C10--C11)) Register FRM_SR16 FRM_SR17 Byte MSB LSB Bit 7--0 7--0 Symbol CNT15--CNT8 CNT7--CNT0 Description CRC-4 Errors at NT1 Counter. CRC-4 Errors at NT1 Counter.
E Bit at NT1 from NT2 Counter Registers (FRM_SR18--FRM_SR19) This register contains the 16-bit count of each occurrence of Sa6 code 00X1, detected synchronously to the CEPT CRC-4 multiframe. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 101. E Bit at NT1 from NT2 Counter (FRM_SR18--FRM_SR19) ((612--613); (C12--C13)) Register FRM_SR18 FRM_SR19 Byte MSB LSB Bit 7--0 7--0 Symbol ENT15--ENT8 ENT7--ENT0 E Bit at NT1 Counter. E Bit at NT1 Counter. Description
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Framer Register Architecture (continued)
The following status registers, FRM_SR20--FRM_SR51, contain the 16-bit count of errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at the ET, ET-RE, NT1, and NT1-RE terminals. DS1 error conditions are reported in the ET errored registers FRM _SR20--FRM_SR35. Table 102. ET Errored Seconds Counter (FRM_SR20--FRM_SR21) ((614--615); (C14--C15)) Register FRM_SR20 FRM_SR21 Byte MSB LSB Bit 7--0 7--0 Symbol ETES15--ETES8 ETES7--ETES0 Description ET Errored Seconds Counter. ET Errored Seconds Counter.
Table 103. ET Bursty Errored Seconds Counter (FRM_SR22--FRM_SR23) ((616--617); (C16--C17)) Register FRM_SR22 FRM_SR23 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETBES15--ETBES8 ET Bursty Errored Seconds Counter. ETBES7--ETBES0 ET Bursty Errored Seconds Counter.
Table 104. ET Severely Errored Seconds Counter (FRM_SR24--FRM_SR25) ((618--619); (C18--C19)) Register FRM_SR24 FRM_SR25 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETSES15--ETSES8 ET Severely Errored Seconds Counter. ETSES7--ETSES0 ET Severely Errored Seconds Counter.
Table 105. ET Unavailable Seconds Counter (FRM_SR26--FRM_SR27) ((61A--61B); (C1A--C1B)) Register FRM_SR26 FRM_SR27 Byte MSB LSB Bit 7--0 7--0 Symbol ETUS15--ETUS8 ETUS7--ETUS0 Description ET Unavailable Seconds Counter Bits. ET Unavailable Seconds Counter Bits.
Table 106. ET-RE Errored Seconds Counter (FRM_SR28--FRM_SR29) ((61C--61D); (C1C--C1D)) Register FRM_SR28 FRM_SR29 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREES15--ETREES8 ET-RE Errored Seconds Counter. ETREES7--ETREES0 ET-RE Errored Seconds Counter.
Table 107. ET-RE Bursty Errored Seconds Counter (FRM_SR30--FRM_SR31) ((61E--61F); (C1E--C1F)) Register FRM_SR30 FRM_SR31 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREBES15--ETREBES8 ET-RE Bursty Errored Seconds Counter. ETREBES7--ETREBES0 ET-RE Bursty Errored Seconds Counter.
Table 108. ET-RE Severely Errored Seconds Counter (FRM_SR32--FRM_SR33) ((620--621); (C20--C21)) Register FRM_SR32 FRM_SR33 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETRESES15--ETRESES8 ET-RE Severely Errored Seconds Counter. ETRESES7--ETRESES0 ET-RE Severely Errored Seconds Counter.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Table 109. ET-RE Unavailable Seconds Counter (FRM_SR34--FRM_SR35) ((622--623); (C22--C23)) Register FRM_SR34 FRM_SR35 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREUS15--ETRESES8 ET-RE Unavailable Seconds Counter. ETRESES7--ETRESES0 ET-RE Unavailable Seconds Counter.
Table 110. NT1 Errored Seconds Counter (FRM_SR36--FRM_SR37) ((624--625); (C24--C25)) Register FRM_SR36 FRM_SR37 Byte MSB LSB Bit 7--0 7--0 Symbol NTES15--NTES8 NTES7--NTES0 Description NT1 Errored Seconds Counter. NT1 Errored Seconds Counter.
Table 111. NT1 Bursty Errored Seconds Counter (FRM_SR38--FRM_SR39) ((626--627); (C26--C27)) Register FRM_SR38 FRM_SR39 Byte MSB LSB Bit 7--0 7--0 Symbol NTBES15--NTBES8 NTBES7--NTBES0 Description NT1 Bursty Errored Seconds Counter. NT1 Bursty Errored Seconds Counter.
Table 112. NT1 Severely Errored Seconds Counter (FRM_SR40--FRM_SR41) ((628--629); (C28--C29)) Register FRM_SR40 FRM_SR41 Byte MSB LSB Bit 7--0 7--0 Symbol NTSES15--NTSES8 NTSES7--NTSES0 Description NT1 Severely Errored Seconds Counter. NT1 Severely Errored Seconds Counter.
Table 113. NT1 Unavailable Seconds Counter (FRM_SR42--FRM_SR43) ((62A--62B); (C2A--C2B)) Register FRM_SR42 FRM_SR43 Byte MSB LSB Bit 7--0 7--0 Symbol NTUS15--NTUS8 NTUS7--NTUS0 Description NT1 Unavailable Seconds Counter Bits. NT1 Unavailable Seconds Counter Bits.
Table 114. NT1-RE Errored Seconds Counter (FRM_SR44--FRM_SR45) ((62C--62D); (C2C--C2D)) Register FRM_SR44 FRM_SR45 Byte MSB LSB Bit 7--0 7--0 Symbol NTREES15--NTREES8 NTREES7--NTREES0 Description NT1-RE Errored Seconds Counter. NT1-RE Errored Seconds Counter.
Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46--FRM_SR47) ((62E--62F); (C2E--C2F)) Register FRM_SR46 FRM_SR47 Byte MSB LSB Bit 7--0 7--0 Symbol Description
NTREBES15--NTREBES8 NT1-RE Bursty Errored Seconds Counter. NTREBES7--NTREBES0 NT1-RE Bursty Errored Seconds Counter.
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Framer Register Architecture (continued)
Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48--FRM_SR49) ((630--631); (C30--C31)) Register FRM_SR48 FRM_SR49 Byte MSB LSB Bit 7--0 7--0 Symbol Description
NTRESES15--NTRESES8 NT1-RE Severely Errored Seconds Counter. NTRESES7--NTRESES0 NT1-RE Severely Errored Seconds Counter.
Table 117. NT1-RE Unavailable Seconds Counter (FRM_SR50--FRM_SR51) ((632--633); (C32--C33)) Register FRM_SR50 FRM_SR51 Byte MSB LSB Bit 7--0 7--0 Symbol NTREUS15--NTREUS8 NTREUS7--NTREUS0 Description NT1-RE Unavailable Seconds Counter Bits. NT1-RE Unavailable Seconds Counter Bits.
Received NOT-FAS TS0 RSa Register (FRM_SR52) This register contains the last (since last read) valid received RSa8--RSa4 bits, A bit, and Si bit of NOT-FAS time slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment. Table 118. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34) Bit 7 NOT-FAS bit 1 (CEPT without CRC-4) or frame 15 E bit (CEPT with CRC-4) Bit 6 FAS bit 1 (CEPT without CRC-4) or frame 13 E bit (CEPT with CRC-4) Bit 5 A bit Bit 4 Sa4 Bit 3 Sa5 Bit 2 Sa6 Bit 1 Sa7 Bit 0 Sa8
Received Sa Register (FRM_SR53) This register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16 signaling multiframe alignment. These bits are updated only when the receive framer is in signaling multiframe alignment. Table 119. Receive Sa Register (FRM_SR53) (635; C35) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 X2 Bit 1 X1 Bit 0 X0
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
SLC-96 FDL/CEPT Sa Receive Stack (FRM_SR54--FRM_SR63)
In the SLC-96 frame format, FRM_SR54 through FRM_SR58 contain the received SLC-96 facility data link data block. When the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers are not updated. Note: The RSP[1:4] are the received spoiler bits. Table 120. SLC-96 FDL Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) Register FRM_SR54 FRM_SR55 FRM_SR56 FRM_SR57 FRM_SR58 FRM_SR59-- FRM_SR61 Bit 7 0 0 RC1 RC9 RM3 0 Bit 6 0 0 RC2 RC10 RA1 0 Bit 5 R-0 R-0 RC3 RC11 RA2 0 Bit 4 Bit 3 Bit 2 Bit 1 R-1 R-1 RC7 RM1 RS4 0 Bit 0 R-1 R-1 RC8 RM2 RSPB4 = 1 0
R-0 R-0 R-1 R-0 R-0 R-1 RC4 RC5 RC6 RSPB1 = 0 RSPB2 = 1 RSPB3 = 0 RS1 RS2 RS3 0 0 0
In the CEPT frame format, FRM_SR54 through FRM_SR63 contain the received Sa4 through Sa8 from the last valid CRC-4 double-multiframe. In non-CRC-4 mode, these registers are only updated during a basic frame-aligned state. In CRC-4 mode, these registers are only updated during the CRC-4 multiframe alignment state. Table 121. CEPT Sa Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) Register FRM_SR54 FRM_SR55 FRM_SR56 FRM_SR57 FRM_SR58 FRM_SR59 FRM_SR60 FRM_SR61 FRM_SR62 FRM_SR63 Bit 7 Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
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Framer Register Architecture (continued)
The receive framer stores the current second of the ANSI Performance Report Message transmitted to the remote end in registers FRM_SR62 and FRM_SR63. The structure of the PRM status registers is shown in Table 122. Table 122. Transmit Framer ANSI Performance Report Message Status Register Structure Transmit Framer PRM Status Bytes FRM_SR62 FRM_SR63 TSPRM B7 TSPRM B6 TSPRM B5 TSPRM B4 TSPRM B3 TSPRM B2 TSPRM B1 TSPRM B0
G3 FE
LV SE
G4 LB
U1 G1
U2 R
G5 G2
SL Nm
G6 Nl
Received Signaling Registers: DS1 Format Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0--FRM_RSR23) ((640--658); (C40--C58)) Received Signal Registers DS1 Received Signaling Registers (0--23) Voice Channel with 16-State Signaling Voice Channel with 4-State Signaling Voice Channel with 2-State Signaling Data Channel Bit 7 Bit 61 P X X X X G 0 0 1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F 0 1 1 0 X X X X X D D X X X C C X X X B B B X X A A A A X
1. Bit 6 and Bit 5 of the DS1 receive signaling registers are copied from bit 6 and bit 5 of the DS1 transmit signaling registers.
Receive Signaling Registers: CEPT Format Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0--FRM_RSR31) ((640--65F); (C40--C5F)) Receive Signal Registers FRM_RSR1--FRM_RSR15 FRM_RSR[17:31] Bit 7 P P Bit 6--5 X X Bit 41 E[1:15] E[17:31] Bit 3 D[1:15] D[17:31] Bit 2 C[1:15] C[17:31] Bit 1 B[1:15] B[17:31] Bit 0 A[1:15] A[17:31]
1. In PCS0 or PCS1 signaling mode, this bit is undefined.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Registers FRM_PR0--FRM_PR70 define the mode configuration of each framer. All are read/write registers. These registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) The bits in this register group enable the status registers FRM_SR0--FRM_SR7 to assert the interrupt pin. The default value of these registers is 00 (hex). FRM_PR0 is the primary interrupt group enable register which enables the event groups in interrupt status register FRM_SR0. A bit set to 1 in this register enables the corresponding bit in the interrupt status register FRM_SR0 to assert the interrupt pin. FRM_PR1--FRM_PR7 are the secondary interrupt enable registers. A bit set to 1 in these registers enables the corresponding bit in the status register to assert the interrupt pin. Table 125. Summary of Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) ((660--667); (C60--C67))
Parameter /Control Register FRM_PR0 Status Register Enabled FRM_SR0 Status Register Bit 7 S96SR Status Register Bit 6 Reserved Status Register Bit 5 RSSFE Status Register Bit 4 TSSFE Status Register Bit 3 ESE (read FRM_SR5, FRM_SR6, and FRM_SR7) LFALR RSa6 = 8 ECE LLBON (CMA) ETUAS NTUAS NROUAS Status Register Bit 2 FAE (read FRM_SR3 and FRM_SR4) LTSFA (LTS0MFA) CREBIT CRCE LLBOFF (BFA) ETSES NTSES NT1OUAS Status Register Bit 1 RAC (read FRM_SR2) Status Register Bit 0 FAC (read FRM_SR1)
FRM_PR1 FRM_PR2 FRM_PR3 FRM_PR4 FRM_PR5 FRM_PR6 FRM_PR7
FRM_SR1 FRM_SR2 FRM_SR3 FRM_SR4 FRM_SR5 FRM_SR6 FRM_SR7
AIS RSa6 = F SLIPU FDL_LLBOFF (TSaSR) ETREUAS NTREUAS RQUASI
AUXP RSa6 = E SLIPO FDL_LLBON (RSaSR) ETRESES NTRESES RPSUEDO
RTS16AIS RSa6 = C LCRCATMX FDL_PLBOFF (SLCTFSR) ETREBES NTREBES PTRNBER
LBFA RSa6 = A REBIT FDL_PLBON (SLCRFSR) ETREES NTREES DETECT
LSFA (LTS16MFA) RJYA (RTS16MFA) FBE SSFA ETBES NTBES EROUAS
LFA RFA LFV CFA ETES NTES OUAS
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Framer Register Architecture (continued)
Primary Interrupt Enable Register (FRM_PR0) The default value of this register is 00 (hex). Table 126. Primary Interrupt Group Enable Register (FRM_PR0) (660; C60) Bit 0 1 2 3 4 5 6 7 Symbol SR1IE SR2IE SR34IE SR567IE TSRIE RSRIE -- SLCIE Description Status Register 1 Interrupt Enable Bit. A 1 enables register FRM_SR1 event interrupts. Status Register 2 Interrupt Enable Bit. A 1 enables register FRM_SR2 event interrupts. Status Registers 3 and 4 Interrupt Enable Bit. A 1 enables registers FRM_SR3 and FRM_SR4 event interrupts. Status Registers 5, 6, and 7 Interrupt Enable Bit. A 1 enables registers FRM_SR5, FRM_SR6, and FRM_SR7 event interrupts. Transmit Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when transmit signaling buffers are ready (MOS mode). Receive Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when receive signaling buffers are ready (MOS mode). Reserved. Write to 0. SLC-96 Interrupt Enable Bit. A 1 enables interrupts when SLC-96 receive or transmit stacks are ready.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Secondary Interrupt Enable Registers (FRM_PR1--FRM_PR7) A bit set to 1 in registers FRM_PR1--FRM_PR7 enables the generation of interrupts whenever the corresponding bit in registers FRM_SR1--FRM_SR7 is set. The default value of these registers is 00 (hex). Table 127. Interrupt Enable Register (FRM_PR1) (661; C61) Bit 0--7 Symbol SR1B0IE-- SR1B7IE Description Status Register 1 Interrupt Enable. A 1 enables events monitored in register FRM_SR1 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 128. Interrupt Enable Register (FRM_PR2) (662; C62) Bit 0--7 Symbol SR2B0IE-- SR2B7IE Description Status Register 2 Interrupt Enable. A 1 enables events monitored in register FRM_SR2 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 129. Interrupt Enable Register (FRM_PR3) (663; C63) Bit 0--7 Symbol SR3B0IE-- SR3B7IE Description Status Register 3 Interrupt Enable. A 1 enables events monitored in register FRM_SR3 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 130. Interrupt Enable Register (FRM_PR4) (664; C64) Bit 0--7 Symbol SR4B0IE-- SR4B7IE Description Status Register 4 Interrupt Enable. A 1 enables events monitored in register FRM_SR4 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 131. Interrupt Enable Register (FRM_PR5) (665; C65) Bit 0--7 Symbol SR5B0IE-- SR5B7IE Description Status Register 5 Interrupt Enable. A 1 enables events monitored in register FRM_SR5 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 132. Interrupt Enable Register (FRM_PR6) (666; C66) Bit 0--7 Symbol SR6B0IE-- SR6B7IE Description Status Register 6 Interrupt Enable. A 1 enables events monitored in register FRM_SR6 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 133. Interrupt Enable Register (FRM_PR7) (667; C67) Bit 0--7 Symbol SR7B0IE-- SR7B7IE Description Status Register 7 Interrupt Enable. A 1 enables events monitored in register FRM_SR7 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register. 165
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Framer Register Architecture (continued)
Framer Mode Option Register (FRM_PR8) The default value of this register is C0 (hex). Table 134. Framer Mode Bits Decoding (FRM_PR8) (668; C68) FRM_PR8 Frame Format ESF D4 DDS DDS with FDL SLC-96 Transmit ESF Receive D4 Transmit D4 Receive ESF CEPT PCS Mode 0 with No CRC-4 PCS Mode 1 CEPT PCS Mode 0 with CRC-4 PCS Mode 1 Bit 7 Bit 6 Bit 5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FMODE4 FMODE3 FMODE2 FMODE1 FMODE0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0
Table 135. Line Code Option Bits Decoding (FRM_PR8) (668; C68) Line Code Format B8ZS (T/R) ZCS (T/R) HDB3 (T/R) Single Rail (DEFAULT) AMI (T/R) B8ZS (T), AMI (R) ZCS (T), B8ZS (R) AMI (T), B8ZS (R) Bit 7 LC2 0 0 0 1 0 1 1 1 Bit 6 LC1 0 0 1 1 1 0 0 1 Bit 5 LC0 0 1 0 0 1 0 1 1 Bit 4 X X X X X X X X Bit 3 X X X X X X X X Bit 2 X X X X X X X X Bit 1 X X X X X X X X Bit 0 X X X X X X X X
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Framer Register Architecture (continued)
Framer CRC Control Option Register (FRM_PR9) This register defines the CRC options for the framer. The default setting is 00 (hex). Table 136. CRC Option Bits Decoding (FRM_PR9) (669, C69) FRM_PR9 CRC Options Loss of Frame Alignment Due to Excessive CRC Errors (ESF 320, CEPT 915 in a one-second interval) CRC-4 with 100 ms Timer CRC-4 Interworking Search with 400 ms Timer CRC-4 with 990 REB Counter CRC-4 with 990 REB Counter: A Bit = 1 Restart CRC-4 with 990 REB Counter: Sa6-F or Sa6-E Restart XCRC-4/R-NO CRC-4 X-NOCRC-4/RCRC4 CRC Default Mode (No CRC) Alarm Filter Register (FRM_PR10) The bits in this register enable various control options. The default setting is 00 (hex). Table 137. Alarm Filter Register (FRM_PR10) (66A; C6A) Bit 0 Symbol SSa6M Description Synchronous Sa6 Monitoring. A 0 enables the asynchronous monitoring of the Sa6 codes relative to the receive CRC-4 submultiframe. A 1 enables synchronous monitoring of the Sa6 pattern relative to the receive CRC-4 submultiframe. AIS Detection Mode. A 0 enables the detection of received line AIS as described in ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as described in ITU Rec. G.775. FER Enable. A 0 enables only the detection of FT framing bit errors in D4 and SLC-96 modes. A 1 enables the detection of FT and FS framing bit errors. CNUCLB Enable. A 0 enables payload loopback with regenerated/CRC bits in register FRM_PR24. A 1 enables CEPT nailed-up connect loopback in register FRM_PR24. Reserved. Set to 0. Bit 7 0 Bit 6 X Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 1 Bit 0 1
0 0 0 0 0 1 1 0
X X X X 1 X X 0
X X X 1 X X X 0
X X 1 1 1 X X 0
X 1 X X X X X 0
1 X X X X X X 0
X X X X X X X 0
1 1 1 1 1 0 1 0
1
AISM
2 3 4--5
FEREN CNUCLBEN --
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Framer Register Architecture (continued)
Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 138 below. The EST parameter refers to the errored second threshold defined in register FRM_PR11. The SEST parameter refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13. Table 138. Errored Event Threshold Definition Bit 7, FRM_PR10 ESM1 0 0 Bit 6, FRM_PR10 ESM0 0 1 Errored Second (ES) Definition Bursty Errored Second (BES) Definition Severely Errored Second (SES) Definition
Other Combinations
Default values in Table 44. Event Counters Definition. ES = 1 when: BES = 0 SES = 1 when: Errored events > EST Errored events > SEST Reserved.
Errored Second Threshold Register (FRM_PR11) This register defines the errored event threshold for an errored second (ES). A one-second interval with errors less than the ES threshold value will not be detected as an errored second. Programming 00 (hex) into this register disables the errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value of this register is 00 (hex). Table 139. Errored Second Threshold Register (FRM_PR11) (66B; C6B) Register FRM_PR11 Symbol EST7--EST0 ES Threshold Register. Description
Severely Errored Second Threshold Register (FRM_PR12--FRM_PR13) This 16-bit register defines the errored event threshold for a severely errored second (SES). A one-second interval with errors less than the SES threshold value is not a severely errored second. Programming 00 (hex) into these two registers disables the severely errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value of these registers is 00 (hex). Table 140. Severely Errored Second Threshold Registers (FRM_PR12--FRM_PR13) ((66C--66D; C6C--C6D)) Register FRM_PR12 FRM_PR13 Symbol SEST15--SEST8 SEST7--SEST0 SES MSB Threshold Register. SES LSB Threshold Register. Description
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
ET1 Errored Event Enable Register* (FRM_PR14) These bits enable the errored events used to determine errored and severely errored seconds at the local ET interface. ETSLIP ETAIS, ETLMFA, and ETLFA are the SLIP AIS, LMFA, and LFA errored events, respectively, as , , referred to the local ET interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 141. ET1 Errored Event Enable Register (FRM_PR14) (66E; C6E) Register FRM_PR14 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 ETSLIP Bit 2 ETAIS Bit 1 ETLMFA Bit 0 ETLFA
ET1 Remote End Errored Event Enable Register* (FRM_PR15) These bits enable the errored events used to determine errored and severely errored seconds at the ET's remote end interface. ETRESa6-F, ETRESa6-E, ETRESa6-8, ETRERFA, ETRESLIP ETREAIS, ETRELMFA, and , ETRELFA are the Sa6-F, Sa6-E, Sa6-8, RFA, SLIP AIS, LMFA, and LFA errored events, respectively, as referred to , the ET remote end interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 142. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FRM_PR15 ETRESa6-F ETRESa6-E ETRESa6-8 ETRERFA ETRESLIP ETREAIS ETRELMFA ETRELFA NT1 Errored Event Enable Register* (FRM_PR16) These bits enable the errored events used to determine errored and severely errored seconds at the network termination-1 interface. NTSa6-C, NTSa6-8, NTSLIP NTAIS, NTLMFA, and NTLFA are the Sa6-C, Sa6-8, SLIP AIS, , , LMFA, and LFA errored events, respectively, as referred to the NT1 interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 143. NT1 Errored Event Enable Register (FRM_PR16) (670; C70) Register FRM_PR16 Bit 7 NTSa6-C Bit 6 0 Bit 5 NTSa6-8 Bit 4 0 Bit 3 NTSLIP Bit 2 NTAIS Bit 1 NTLMFA Bit 0 NTLFA
NT1 Remote End Errored Event Enable Register* (FRM_PR17--FRM_PR18) These bits enable the errored events used to determine errored and severely errored seconds at the network termination-1 remote end interface. NTRERFA, NTRESLIP NTREAIS, NTRELMFA, NTRELFA, NTRESa6-C, , NTRESa6-F, NTRESa6-E, and NTRESa6-8 are the RFA, SLIP AIS, LMFA, LFA, Sa6-C, Sa6-F, Sa6-E, and Sa6-8 , errored events, respectively, as referred to the NT-1 remote end interface. The default value of this register is 00 (hex). Table 144. NT1 Remote End Errored Event Enable Registers (FRM_PR17--FRM_PR18) ((671--672); (C71--C72)) Register FRM_PR17 FRM_PR18 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NTRERFA NTRESLIP NTREAIS NTRELMFA NTRELFA 0 NTRESa6-C NTRESa6-F NTRESa6-E NTRESa6-8
* One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.
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Framer Register Architecture (continued)
Automatic AIS to the System and Automatic Loopback Enable Register The default value of this register is 00 (hex). Table 145. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) Bit 0 1 Symbol ASAIS ASAISTMX Description Automatic System AIS. A 1 transmits AIS to the system whenever the receive framer is in the loss of receive frame alignment (RLFA) state. Automatic System AIS CEPT CRC-4 Timer Expiration. A 1 transmits AIS to the system after the CRC-4 100 ms or 400 ms timer expires. AIS is transmitted for the duration of the loss of CRC-4 multiframe alignment state. Reserved. Set to 0. Transmit System AIS. A 1 transmits AIS to the system. Automatic Line Loopback Enable. A 1 enables the framer section to execute the DS1 line loopback on or off commands without system intervention. Reserved. Set to 0. Automatic FDL Line Loopback Enable. A 1 enables the framer section to execute a line ESF FDL loopback on or off command without system intervention. Automatic FDL Payload Loopback Enable. A 1 enables the framer section to execute a payload ESF FDL loopback on or off command without system intervention.
2 3 4 5 6 7
-- TSAIS ALLBE -- AFDLLBE AFDPLBE
Transmit Test Pattern to the Line Enable Register* This register enables the transmit framer to transmit various test signals to the line interface. The default value of this register is 00 (hex). Note that between enabling the transmission of line loopback on and off codes this register must be set to 00 (hex) (i.e., to enable transmission of line loopback on code and then off code, write into this register 10 (hex), then 00 (hex), and finally 20 (hex)). Table 146. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74) Bit 0 1 2 3 4 5 6 7 Symbol TUFAIS TUFAUXP TPRS TQRS TLLBON TLLBOFF TLIC TICRC Description Unframed AIS to Line Interface (All Ones Pattern). Unframed AUXP to Line Interface in CEPT Mode (Alternating 010101 Unframed Pattern). Transmit Pseudorandom Signal to Line Interface (215 - 1). Transmit Quasi-Random Signal to Line Interface (220 - 1) (ANSI T1.403). Transmit Framed Payload Line Loopback On Code: 00001. Transmit Framed Payload Line Loopback Off Code: 001. Transmit Line Idle Code of FRM_PR22. When this bit = 1, the line idle code of FRM_PR22 is transmitted to the line in all time slots. Transmit Inverted CRC.
* To transmit test signals using this register, registers FRM_PR69 and FRM_PR70 must be set to 00 (hex).
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Framer FDL Control Command Register (FRM_PR21) The default value of this register is 00 (hex). Table 147. Framer FDL Control Command Register (FRM_PR21) (675; C75) Bit 0 1 2 3 4 5 6 Symbol -- -- -- -- TFDLLAIS TFDLSAIS TFDLC Description Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0. Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link. Transmit Facility Data Link AIS to the System. A 1 sends AIS in the system data link side. Transmit FDL Control Bit. A 0 enables the transmission of the FDL bit from the internal FDL-HDLC unit (default). A 1 enables the transmission of the FDL bit from either TFDL input (pin 67 and 115) or from the internal transmit stack depending on the state of FRM_PR29 bit 5--bit 7. When the SLC-96 stack transmission is enabled (register FRM_PR26 bit 5--bit 7 = x10 (binary), the FDL bit is sourced from the SLC-96 transmit stack (register FRM_PR31--FRM_PR35). Otherwise, it is sourced from TFDL (pins 67/115). Transmit ESF_PRM C/R = 1 (TC/R = 1). A 0 transmits the ESF performance report message with the C/R bit = 0. (See ANSI T1.403-1995 for the PRM structure and content.) A 1 transmits the ESF performance report message with the C/R bit = 1.
7
TC/R = 1
Framer Transmit Line Idle Code Register (FRM_PR22) The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex). Table 148. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76) Bit 0--7 Symbol TLIC0--TLIC7 Description Transmit Line Idle Code 0--7. These 8 bits define the idle code transmitted to the line.
Framer System Stuffed Time-Slot Code Register (FRM_PR23) The value programmed in this register is transmitted in the stuffed time slots on the CHI in the DS1 modes. The default value is 7F (hex). Table 149. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77) Bit 0--7 Symbol SSTSC0-- SSTSC7 Description System Stuffed Time-Slot Code 0--7. These 8 bits define the idle code transmitted in the stuffed time slots to the system (CHI).
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Framer Register Architecture (continued)
Primary Loopback Mode Control and Time-Slot Address (FRM_PR24) This register contains the loopback mode control and the 5-bit address of the line or system time slot to be looped back. The default value is 00 (hex) (no loopback). Table 150. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78) Bit 0--4 5--7 Symbol TSLBA0-- TSLBA4 LBC0--LBC2 Time-Slot Loopback Address. Loopback Control Bits[2:0]. Description
Table 151. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7--5 LBC2 0 0 0 0 LBC1 0 0 1 1 LBC0 0 1 0 1 Function No Loopback. Line Loopback (LLB). The received line data is looped back to the transmit line data. Board Loopback (BLB). The received system data is looped back to the transmit system data, and AIS is sent as the line transmit data. Single Time-Slot System Loopback (STSSLB). System (CHI) loopback of the time slot selected by bit 4--bit 0. Idle code selected by FRM_PR22 is inserted in the line payload in place of the looped back time slot. Single Time-Slot Line Loopback (STSSLB). Line loopback of time slot selected by bit 4--bit 0. Idle code selected by FRM_PR22 is inserted in the system (CHI) payload in place of the looped back time slot. CEPT Nailed-Up Broadcast Transmission (CNUBT). Time slot selected by bit 4-- bit 0 is transmitted normally and also placed into time slot 0. Payload Line Loopback with Regenerated Framing and CRC Bits. This mode is selected if FRM_PR10 bit 3 = 0. The received channelized-payload data is looped backed to the line. The framing bits are generated within the transmit framer. The regenerated framing information includes the F-bit pattern, the CRC checksum bit, and the system's facility data link bit stream. This loopback mode can be used with the CEPT framing mode. The entire time slot 0 data (FAS and NOT FAS) is regenerated by the transmit framer. The receive framer processes and monitors the incoming line data normally in this loopback mode and transmits the formatted data to the system in the normal format via the CHI. CEPT Nailed-Up Connect Loopback (CNUCLB). The received system time slot selected by this register bit 4--bit 0 is looped back to the system in time slot 0. This mode is selected if FRM_PR10 bit 3 = 1. Payload Line Loopback with Passthrough Framing and CRC Bits. The received channelized/payload data, the CRC bits, and the frame alignment bits are looped back to the line. The system's facility data link bit stream is inserted into the looped back data and transmitted to the line. In ESF, the FDL bits are ignored when calculating the CRC-6 checksum. In CEPT, the FDL bits are included when calculating the CRC-4 checksum, and as such, this loopback mode generates CRC-4 errors back at the remote end.
1
0
0
1 1
0 1
1 0
1
1
1
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Framer Register Architecture (continued)
Secondary Loopback Control and ID and Address (FRM_PR25) This register allows for a second single-time-slot loopback mode. This loopback is valid if the secondary time-slot loopback address is different from the primary loopback address and the device is not in a line, board, or payload loopback, see FRM_PR24. This register contains the secondary loopback mode control and the 5-bit address for the secondary line or system time slot to be looped back to the line or system. The default value is 00 (hex) (no loopback). Table 152. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79) Bit 0--4 5--6 7 Symbol STSLBA0--STSLBA4 SLBC0--SLBC1 -- Description Secondary Time-Slot Loopback Address. Secondary Loopback Control Bits[1:0]. Reserved. Write to 0.
Table 153. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6--5 LBC1 0 0 1 1 LBC0 0 1 0 1 Function No Loopback. Secondary Single Time-Slot System Loopback. Secondary Single Time-Slot Line Loopback. Reserved.
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Framer Register Architecture (continued)
Framer Reset and Transparent Mode Control Register (FRM_PR26) The default value of this register is 00 (hex). Table 154. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A) Bits 0 Symbol SWRESET Description
1
2
3
Framer Software Reset. The framer and FDL sections are placed in the reset state for four clock cycles of the frame internal line clock (RFRMCK). The parameter registers are forced to the default values. This bit is self-cleared. SWRESTART Framer Software Restart. The framer and FDL sections are placed in the reset state as long as this bit is set to 1. The framer's parameter registers are not changed from their programmed state. The FDL parameter registers are changed from their programmed state. This bit must be cleared. Framer Reframe. A 0-to-1 transition of this bit forces the receive framer into the loss of FRFRM frame alignment (LFA) state which forces a search of frame alignment. Subsequent reframe commands must have this bit in the 0 state first. Transparent Framing Mode 1. A 1 forces the transmit framer to pass system data TFM1 unmodified to the line and the receive framer to pass line data unmodified to the system. The receive framer is forced not to align to the input receive data. DS1: register FRM_PR43 bit 2--bit 0 must be set to 000. The F bit is located in time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this bit in the F-bit position of the transmit line data. The receive framer inserts the bit in the F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA. CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. Receive line time slot 0 is inserted into time slot 0 of TCHIDATA. Transparent Framing Mode 2. A 1 forces the transmit framer to pass system data unmodified to the line. The receive framer functions normally as programmed. DS1: register FRM_PR43 bit 2--bit 0 must be set to 000. The F bit is located in time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this bit in the F-bit position of the transmit line data.
4
TFM2
5
SYSFSM
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. System Frame Sync Mask. A 1 masks the system frame synchronization signal in the transmit framer section. Note: The transmit framer must see at least one valid system synchronization pulse to initialize its counts; afterwards, this bit may be set. For those applications that have jitter on the transmit clock signal relative to the system clock signal, enable this bit so that the jitter is isolated from the transmit framer. Reserved. Write to 0.
6--7
--
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Automatic and Manual Transmission of the Remote Frame Alarm Control Register (FRM_PR27) The default value of this register is 00 (hex). Table 155. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 Control Register (FRM_PR27) (67B, C7B) Bit 0 1 Symbol ARLFA Description
2 3
4 5 6 7
Automatic Remote Frame Alarm on LFA (ARLFA). A 1 transmits the remote frame alarm to the line whenever the receive framer detects loss of frame alignment (RLFA). AAB16LMFA Automatic A Bit on LMFA (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects loss of time slot 16 signaling multiframe alignment (RTS16LMFA). AAB0LMFA Automatic A Bit on LMFA (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects loss of time slot 0 multiframe alignment (RTS0LMFA). Automatic A Bit on CRC-4 Multiframe Reframer Timer Expiration (CEPT Only). A 1 ATMRX transmits A = 1 to the line when the receive framer detects the expiration of either the 100 ms or 400 ms timers due to loss of multiframe alignment. AARSa6_8 Automatic A Bit on RSa6_8 (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects the Sa6 = 1000 pattern. AARSa6_C Automatic A Bit on RSa6_C (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects the Sa6 = 1100 pattern. Transmit D4 Japanese Remote Frame Alarm. A 1 transmits a valid Japanese remote TJRFA frame alarm for the D4 frame format. Transmit Remote Frame Alarm. A 1 transmits a valid remote frame alarm for the correTRFA sponding frame format.
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Framer Register Architecture (continued)
Automatic and Manual Transmission of E Bit = 0 Control Register The default value of this register is 00 (hex). Table 156. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C) Bit 0 Symbol SIS Description
1 2 3 4
5
6--7
Si-Bit Source. In CEPT with NO CRC-4 mode, a 1 transmits TSiF and TSiNF in the Si bit position to the line in FAS and NOT FAS, respectively. A 0, in non-CRC-4 mode, transmits system Si data to the line transparently*. Transmit One E = 0. In CEPT with CRC-4 mode, a 0 transmits E = TSiF in frame 13 and T1E E = TSiNF in frame 15. A 1 transmits one E bit = 0 for each write access to TSiF = 0 or TSiNF = 0. Transmit Bit 1 in FAS. In CEPT with no CRC-4, this bit can be transmitted to the line in TSiF bit 1 of the FAS. In CRC-4 mode, this bit is used for E-bit data in frame 13. Transmit Bit 1 in NOT FAS. In CEPT with no CRC-4, this bit can be transmitted to the TSiNF line in bit 1 of the NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15. ATERCRCE Automatic Transmit E Bit = 0 for Received CRC-4 Errored Events. A 1 transmits E = 0 to the line whenever the receive framer detects a CRC-4 errored checksum. ATELTS0MFA Automatic Transmit E Bit = 0 for Received Loss of CRC-4 Multiframe Alignment. A 1 transmits E = 0 to the line whenever the receive framer detects a loss of CRC-4 multiframe alignment condition. Automatic Transmit E Bit = 0 on Expiration of CEPT CRC-4 Loss of Multiframe ATERTX Timer. A 1 transmits E = 0 to the line whenever the receive framer detects the expiration of either the 100 ms or 400 ms timer due to the loss of CRC-4 multiframe alignment. These Bits Are Zero. --
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Sa4--Sa8 Source Register (FRM_PR29) These bits contain the fixed transmit Sa bits and define the source of the Sa bits. The default value of this register is 00 (hex). Table 157. Sa4--Sa8 Source Register (FRM_PR29) (67D; C7D) Bit 0--4 5--7 Symbol TSa4--TSa8 SaS5--SaS7 Transmit Sa4--Sa8 Bit. Sa Source Control Bits[2:0]. Description
Table 158. Sa Bits Source Control for Bit 5--Bit 7 in FRM_PR29 SaS7 1 SaS6 0 SaS5 0 Function A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced by this register bit 0--bit 4 if enabled in register FRM_PR30, or transparently from the system interface*. A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are transmitted transparently from the system interface*. A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced from the transmit Sa stack registers (FRM_PR31--FRM_PR40) if enabled in register FRM_PR30, or transparently from the system interface*. SLC-96 Mode. Transmit SLC-96 stack and the SLC-96 interrupts are enabled. The SLC-96 FDL bits are sourced from the transmit SLC-96 stack, registers FRM_PR31-- FRM_PR40. CEPT Mode. Transmit Sa stack and the Sa interrupts are enabled. The Sa bits are sourced from the transmit Sa stack (FRM_PR31--FRM_PR40) if enabled in register FRM_PR30, or transparently from the system interface*. Sa[4:8] bits are transmitted from the system interface transparently through the framer*. Sa[4:8] bits are sourced by bit 0--bit 4 of this register if enabled in register FRM_PR30, or transparently from the system interface*.
1
0
1
1
1
x
0
1
x
0 0
0 0
1 0
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
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Framer Register Architecture (continued)
Sa4--Sa8 Control Register (FRM_PR30) In conjunction with FRM_PR29 bit 5--bit 7, these bits define the source of the individual Sa4--Sa8 bits. The default value of this register is 00 (hex). Table 159. Sa4--Sa8 Control Register (FRM_PR30) (67E; C7E) Bit 0--4 Symbol TESa4--TESa8 Description Transparent Enable Sa4--Sa8 Bit Mask. A 1 enables the transmission of the corresponding Sa bits from the Sa source register (FRM_PR29 bit 0--bit 4) or from the transmit Sa stack. A 0 allows the corresponding Sa bit to be transmitted transparently from the system interface. Reserved. Write to 0. Transmit Double NOTFAS System Time Slot. A 0 enables the transmission of the FAS and NOTFAS on the TCHIDATA interface. A 1 enables the NOTFAS to be transmitted twice on the TCHIDATA interface, and the received time slot 0 from the RCHIDATA is assumed to carry NOTFAS data that is repeated twice.
5--6 7
-- TDNF
Sa Transmit Stack Register (FRM_PR31--FRM_PR40) In CEPT frame format, registers FRM_PR31--FRM_PR40 are used to program the Sa bits in the CEPT multiframe NOT-FAS words. If CRC-4 is enabled, this data is transmitted to the line synchronously to the CRC-4 multiframe. The default value of these registers is 00 (hex). Table 160. Sa Transmit Stack (FRM_PR31--FRM_PR40) ((67F--688); (C7F--C88)) Register FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36 FRM_PR37 FRM_PR38 FRM_PR39 FRM_PR40 Bit 7 Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Architecture (continued)
SLC-96 Transmit Stack (FRM_PR31--FRM_PR40)
In SLC-96 frame format, registers FRM_PR31--FRM_PR35 are used to source the transmit facility data link bits in the FS bit positions. The default value of these registers is 00 (hex). Table 161. SLC-96 Transmit Stack (FRM_PR31--FRM_PR40) ((67F--688); (C7F--C88)) Register FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36-- FRM_PR40 Bit 7 0 0 XC1 XC9 XM3 0 Bit 6 0 0 XC2 XC10 XA1 0 Bit 5 X-0 X-0 XC3 XC11 XA2 0 Bit 4 Bit 3 Bit 2 Bit 1 X-1 X-1 XC7 XM1 XS4 0 Bit 0 X-1 X-1 XC8 XM2 XSPB4 = 1 0
X-0 X-0 X-1 X-0 X-0 X-1 XC4 XC5 XC6 XSPB1 = 0 XSPB2 = 1 XSPB3 = 0 XS1 XS2 XS3 0 0 0
In SLC-96 frame format, the bits in registers FRM_PR31--FRM_PR35 are transmitted using the format shown in Table 164. Table 162. Transmit SLC-96 FDL Format
FS = 000111000111 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XC8 XC9 XC10 XC11 XSPB1 XSPB2 XSPB3 XM1 XM2 XM3 XA1 XA2 XS1 XS2 XS3 XS4 XSPB4
CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) The default value of this register is 00 (hex). Table 163. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) (689; C89) Bit 0--2 3 4 Symbol Description
5 6 7
TTS16X0--TTS16X2 Transmit Time Slot 16 X0--X2 Bits. The content of these bits are written into CEPT signaling multiframe time slot 16 X bits. X-Bit Source. A 1 enables the TTS16X[2:0] bits to be written into CEPT time slot XS 16 signaling multiframe frame. A 0 transmits the X bits transparently. Automatic Line Transmit Time Slot 16 Remote Multiframe Alarm. A 1 ALTTS16RMFA enables the transmission of CEPT time slot 16 signaling remote multiframe alarm when the receive framer is in the loss of CEPT signaling (RTS16LMFA) state. Transmit Line Time Slot 16 Remote Multiframe Alarm. A 1 enables the transTLTS16RMFA mission of CEPT time slot 16 signaling remote multiframe alarm. Transmit Line Time Slot 16 AIS. A 1 enables the transmission of CEPT time slot TLTS16AIS 16 alarm indication signal. Reserved. Write to 0. --
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Framer Register Architecture (continued)
Framer Exercise Register (FRM_PR42) This register is used for exercising the device in a test mode. In normal operation, it and should be set to 00 (hex). The default value of this register is 00 (hex). Table 164. Framer Exercise Register (FRM_PR42) (68A; C8A) Bit FEX0--FEX5 FEX6 FEX7 0 0 0 1 1 0 1 1 Description Framer Exercise Bits 0--5 (FEX0--FEX5). See Table 167. Second Pulse Interval. 1 Second Pulse. 500 ms Pulse. 100 ms Pulse. Reserved.
Table 165. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (68A; C8A) Exercise Type Facility Status FEX5 FEX4 FEX3 FEX2 0 0 1 0 FEX1 FEX0 0 0 Exercise Line format violation CRC checksum error Receive remote frame alarm Alarm indication signal detection Loss of frame alignment Receive remote frame alarm Time slot 0 1-bit shift Transmit corrupt CRC Frame-bit error & loss of frame alignment Loss of time slot 16 multiframe alignment Remote frame alarm CRC bit errors Frame-bit errors Frame-bit errors & loss of frame alignment Loss of time slot 16 multiframe alignment Frame-bit error & loss of frame alignment Change of frame alignment Framing Format All ESF or CEPT D4 or ESF All CEPT Japanese D4 CEPT ESF & CEPT All CEPT D4 & DDS ESF & CEPT All All CEPT All
0
0
1
0
0
1
0 0
0 0
1 1
0 0
1 1
0 1
0 0
0 0
1 1
1 1
0 0
0 1
0
0
1
1
1
0
0 0
0 0
1 0
1 0
1 0
1 0
ESF, DDS & CEPT Loss of time slot 16 multiframe align- CEPT ment Excessive CRC checksum errors ESF & CEPT No test mode activated
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Table 165. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (68A; C8A) (continued) Exercise Type Performance Status FEX5 FEX4 FEX3 FEX2 0 0 0 0 0 0 0 0 Status Counters 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 FEX1 FEX0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Exercise Errored second Bursty errored second Severely errored second Severely errored second count Unavailable state Factory test Increment status counters SR6--SR14 Increment status counters SR6--SR14 CRC error counter Errored event counter Errored second counter Severely errored second counter Unavailable second counter Line format violation counter Frame bit error counter Reserved Framing Format All
--
0 0 0 0 0 1 X 0 1 0 1 0 0 1 0 0 1 1 0 1 1 All other combinations
All
--
DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) The default value of this register is 00 (hex). Table 166. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B) Bit 0--2 Symbol Description
3 4--7
STS0--STS2 In DS1 mode, bit 0--bit 2 program the positions of the stuffed time slots on the CHI. The content of the stuffed time slot can be programmed using register FRM_PR23. Bits 210 000 = SDDDSDDDSDDDSDDDSDDDSDDDSDDDSDDD 001 = DSDDDSDDDSDDDSDDDSDDDSDDDSDDDSDD 010 = DDSDDDSDDDSDDDSDDDSDDDSDDDSDDDSD 011 = DDDSDDDSDDDSDDDSDDDSDDDSDDDSDDDS 100 = DDDDDDDDDDDDDDDDDDDDDDDDSSSSSSSS SaFDL0-- In CEPT mode, bit 0--bit 2 program the Sa bit source of the facility data link. SaFDL2 Bits 210 000: Sa4 = FDL 001: Sa5 = FDL 010: Sa6 = FDL 011: Sa7 = FDL 100: Sa8 = FDL In both DS1 and CEPT modes, only the bit values shown above may be selected. SSC SLC-96 Signaling Control (DS1 Only). A 1 enables the SLC-96 9-state signaling mode. A 0 enables 16-state signaling in the SLC-96 framing mode. Reserved. Write to 0. -- 181
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Preliminary Data Sheet October 2000
Framer Register Architecture (continued)
Signaling Mode Register (FRM_PR44) This register programs various signaling modes. The default value is 00 (hex). Table 167. Signaling Mode Register (FRM_PR44) (68C; C8C) Bit 0 Symbol TSIG Description Transparent Signaling. A 0 enables signaling information to be inserted into and extracted from the data stream. The signaling source is either the signaling registers or the system data (in the associated signaling mode). In DS1 modes, the choice of data or voice channels assignment for each channel is a function of the programming of the F and G bits in the transmit signaling registers. A 1 enables data to pass through the device transparently. All channels are treated as data channels. Stomp Mode. A 0 allows the received signaling bits to pass through the receive signaling circuit unmodified. In DS1 robbed-bit signaling modes, a 1 enables the receive signaling circuit to replace (in those time slots programmed for signaling) all signaling bits (in the receive line bit stream) with a 1, after extracting the valid signaling information. In CEPT time slot 16 signaling modes, a 1 enables the received signaling circuit substitute of the signaling combination of ABCD = 0000 to ABCD = 1111. Associated Signaling Mode. A 1 enables the associate signaling mode which configures the CHI to carry both data and its associated signaling information. Enabling this mode must be in conjunction with the programming of the CHI data rate to 4.096 Mbits/s or 8.192 Mbit/s. Each channel consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. Receive Signaling Inhibit. A 1 inhibits updating of the receive signaling buffer. Message-Oriented Signaling. DS1: A 1 enables the channel 24 message-oriented signaling mode. TSR-ASM Mode (DS1 Only). In the DS1 mode, setting this bit and FRM_PR44 bit 2 (ASM) to 1 enables the transmit signaling register F and G bits to define the robbed-bit signaling format while the ABCD bit information is extracted from the CHI interface. The F and G bits are copied to the receive signaling block and are used to extract the signaling information from the receive line. Automatic System Transmit Signaling AIS (CEPT Only). A 1 transmits AIS in system time slot 16 during receive loss of time slot 16 signaling multiframe alignment state. Transmit CEPT System Signaling Squelch (CEPT Only). AIS is transmitted in time slot 16 of the transmit system data.
1
STOMP
2
ASM
3 4 5
RSI MOS TSR-ASM
6 7
ASTSAIS TCSS
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
CHI Common Control Register (FRM_PR45) These bits define the common attributes of the CHI for TCHIDATA, TCHIDATAB, RCHIDATA, and RCHDATAB. The default value of this register is 00 (hex). Table 168. CHI Common Control Register (FRM_PR45) (68D; C8D) Bit 0 Symbol HFLF Description High-Frequency/Low-Frequency PLLCK Clock Mode. A 0 enables the low-frequency PLLCK mode for the divide down circuit in the internal phase-lock loop section (DS1 PLLCK = 1.544 MHz; CEPT PLLCK = 2.048 MHz). The divide down circuit will produce an 8 kHz signal on DIV-PLLCK, pin 6 and pin 32. A 1 enables the high-frequency PLLCK mode for the divide down circuit in the internal phase-lock loop section (DS1: PLLCK = 6.176 (4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide down circuit will produce a 32 kHz signal on DIV-PLLCK. Concentration Highway Clock Mode. A 0 enables the CHI clock frequency and CHI data rate to be equal. Function fo CMS =1 is reserved. This control bit affects both the transmit and receive interfaces. Concentration Highway Interface Data Rate Select. Bits CHI Data Rate 23 00 2.048 Mbits/s 01 4.096 Mbits/s 10 8.192 Mbits/s 11 Reserved Concentration Highway Master Mode. A 0 enables external system's frame synchronization signal (TCHIFS) to drive the transmit path of the framer's concentration highway interface. A 1 enables the framer's transmit concentration interface to generate a system frame synchronization signal derived from the receive line interface. The framer's system frame synchronization signal is generated on the TCHIFS output pin. Applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the TCHIFS signal generated by the framer. The receive CHI path is not affected by this mode. Reserved. Write to 0. Highway Enable. A 1 in this bit position enables transmission to the concentration highway. This allows the T7630 to be fully configured before transmission to the highway. A 0 forces the idle code as defined in register FRM_PR22 to be transmitted to the line in all payload time slots and the transmit CHI pin is forced to a high-impedance state for all CHI transmitted time slots.
1
CMS
2--3
CDRS0-- CDRS1
4
CHIMM
5--6 7
-- HWYEN
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Framer Register Architecture (continued)
CHI Common Control Register (FRM_PR46) This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex). Table 169. CHI Common Control Register (FRM_PR46) (68E; C8E) Bit 0--2 Symbol TOFF0-- TOFF2 TFE ROFF0-- ROFF2 RFE Description Transmit CHI Bit Offset. These 3 bits define the bit offset from TCHIFS for each transmit time slot. The offset is the number of TCHICK clock periods by which the first bit is delayed from TCHIFS. Transmit Frame Clock Edge. A 0 (1) enables the falling (rising) edge of TCHICK to latch in the frame synchronization signal, TCHIFS. Receive CHI Bit Offset. These 3 bits define the bit offset from RCHIFS for each received time slot. The offset is the number of RCHICK clock periods by which the first bit is delayed from RCHIFS. Received Frame Clock Edge. A 0 (1) enables the falling (rising) edge of RCHICK to latch in the frame synchronization signal, RCHIFS.
3 4--6
7
CHI Transmit Control Register (FRM_PR47) The default value of this register is 00 (hex). Table 170. CHI Transmit Control Register (FRM_PR47) (68F; C8F) Bit 0--5 Symbol TBYOFF0-- TBYOFF5 TCE -- Description Transmit Byte Offset. Combined with FRM_PR65 bit 0 (TBYOFF6), these 6 bits define the byte offset from TCHIFS to the beginning of the next transmit CHI frame on TCHIDATA. Transmitter Clock Edge. A 1 (0) enables the rising (falling) edge of TCHICK to clock out data on TCHIDATA. Reserved. Write to 0.
6 7
CHI Receive Control Register (FRM_PR48) The default value of this register is 00 (hex). Table 171. CHI Receive Control Register (FRM_PR48) (690; C90) Bit 0--5 Symbol RBYOFF0-- RBYOFF5 RCE -- Description Receiver Byte Offset. Combined with FRM_PR66 bit 0 (RBYOFF6), these 6 bits define the byte offset from RCHIFS to the beginning of the next receive CHI frame on RCHIDATA. Receiver Clock Edge. A 1 (0) enables the rising (falling) edge of RCHICK to latch data on RCHIDATA. Reserved. Write to 0.
6 7
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) These four registers define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex). Table 172. CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) ((691--694); (C91--C94)) Register FRM_PR49 FRM_PR50 FRM_PR51 FRM_PR52 Bit 7--0 7--0 7--0 7--0 Symbol TTSE31--TTSE24 TTSE23--TTSE16 TTSE15--TTSE8 TTSE7--TTSE0 Description Transmit Time-Slot Enable Bits 31--24. Transmit Time-Slot Enable Bits 23--16. Transmit Time-Slot Enable Bits 15--8. Transmit Time-Slot Enable Bits 7--0.
CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) These four registers define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHIDATAB time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to the line in the corresponding time slot. The default value of this register is FF (hex). Table 173. CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) ((695--698); (C95--C98)) Register FRM_PR53 FRM_PR54 FRM_PR55 FRM_PR56 Bit 7--0 7--0 7--0 7--0 Symbol RTSE31--RTSE24 RTSE23--RTSE16 RTSE15--RTSE8 RTSE7--RTSE0 Description Receive Time-Slot Enable Bits 31--24. Receive Time-Slot Enable Bits 23--16. Receive Time-Slot Enable Bits 15--8. Receive Time-Slot Enable Bits 7--0.
CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) These four registers define which transmit CHI highway TCHIDATA or TCHIDATAB contains valid data for the active time slot. A 0 enables TCHIDATA, and a 1 enables TCHIDATAB. The default value of this register is 00 (hex). Table 174. CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) ((699--69C); (C99--C9C)) Register FRM_PR57 FRM_PR58 FRM_PR59 FRM_PR60 Bit 7--0 7--0 7--0 7--0 Symbol THS31--THS24 THS23--THS16 THS15--THS8 THS7--THS0 Description Transmit Highway Select Bits 31--24. Transmit Highway Select Bits 23--16. Transmit Highway Select Bits 15--8. Transmit Highway Select Bits 7--0.
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Framer Register Architecture (continued)
CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) These four registers define which receive CHI highway RCHIDATA or RCHIDATAB contains valid data for the active time slot. A 0 enables RCHIDATA, and a 1 enables RCHIDATAB. The default value of these registers is 00 (hex). Table 175. CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) ((69D--6A0); (C9D--CA0)) Register FRM_PR61 FRM_PR62 FRM_PR63 FRM_PR64 Bit 7--0 7--0 7--0 7--0 Symbol RHS31--RHS24 RHS23--RHS16 RHS15--RHS8 RHS7--RHS0 Description Receive Highway Select Bits 31--24. Receive Highway Select Bits 23--16. Receive Highway Select Bits 15--8. Receive Highway Select Bits 7--0.
CHI Transmit Control Register (FRM_PR65) The default value of this register is 00 (hex). Table 176. CHI Transmit Control Register (FRM_PR65) (6A1; CA1) Bit 0 Symbol TBYOFF6 Description Transmit CHI 64-Byte Offset. A 1 enables a 64-byte offset from TCHIFS to the beginning of the next transmit CHI frame on TCHIDATA. A 0 enables a 0-byte offset (if bit 0-- bit 5 of FRM_PR47 = 0). Combing bit 0--bit 5 of FRM_PR47 with this bit allows programming the byte offset from 0--127. Transmit CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot mode. In this mode, the TCHI clock runs at twice the rate of TCHIDATA. Reserved. Write to 0.
1 2--7
TCHIDTS --
CHI Receive Control Register (FRM_PR66) The default value of this register is 00 (hex). Table 177. CHI Receive Control Register (FRM_PR66) (6A2; CA2) Bit 0 Symbol RBYOFF6 Description Receive CHI 64-Byte Offset. A 1 enables a 64-byte offset from RCHIFS to the beginning of the next receive CHI frame on RCHIDATA. A 0 enables a 0-byte offset (if bit 0-- bit 5 of FRM_PR48 = 0). Combing bit 0--bit 5 of FRM_PR48 with this bit allows programming the byte offset from 0--127. Receive CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot mode. In this mode, the RCHI clock runs at twice the rate of RCHIDATA. Reserved. Write to 0.
1 2--7
RCHIDTS --
Reserved Parameter/Control Registers Registers FRM_PR67 and FRM_PR68, addresses 6A3 and 6A4 or CA3 and CA4, are reserved. Write these registers to 0.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Auxiliary Pattern Generator Control Register (FRM_PR69) The following register programs the auxiliary pattern generator in the transmit framer. The default value of this register is 00 (hex). Table 178. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5)* Bit 0 1 Symbol ITD TPEI Description
Invert Transmit Data. Setting this bit to 1 inverts the transmitted pattern. Test Pattern Error Insertion. Toggling this bit from a 0 to a 1 inserts a single bit error in the transmitted test pattern. 2 GBLKSEL Generator Block Select. Setting this bit to 1 enables the generation of test patterns in this register. 3 GFRMSEL Generator Frame Test Pattern. Setting this bit to 1 results in the generation of an unframed pattern. A 0 results in a framed pattern (T1 and CEPT). 4-- GPTRN0-- Generator Pattern Select. These 4 bits select which random pattern is to be transmitted. 7 GPTRN3 Description Bits Generator Standard 7654 Polynomial -- MARK (all ones) (AIS) 0000 -- QRSS (220 - 1 with zero 0001 1+x-17+x-20 O.151 suppression) 0010 25 - 1 -- 1+x-3+x-5 0011 -- 63 (26 - 1) 1+x-1+x-6 0100 O.153 511 (29 - 1) 1+x-5+x-9 0101 -- 511 (29 - 1) reversed 1+x-4+x-9 0110 O.152 2047 (211 - 1) 1+x-9+x-11 0111 -- 2047 (211 - 1) reversed 1+x-2+x-11 1000 O.151 215 - 1 1+x-14+x-15 1001 O.153 220 - 1 1+x-3+x-20 1010 CB113/CB114 220 - 1 1+x-17+x-20 1011 O.151 223 - 1 1+x-18+x-23 1100 -- 1:1 (alternating) --
* To generate test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).
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Preliminary Data Sheet October 2000
Framer Register Architecture (continued)
Pattern Detector Control Register (FRM_PR70) The following register programs the pattern detector in the receive framer. The default value of this register is 00 (hex). Table 179. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)* Bit 0 Symbol IRD Description
Invert Receive Data. Setting this bit to 1 enables the pattern detector to detect the inverse of the selected pattern. Reserved. Write to 0. 1 -- 2 DBLKSEL Detector Block Select. Setting this bit to 1 enables the detection of test patterns in this register. 3 DUFTP Detect Unframed Test Pattern. Setting this bit to 1 results in the search for an unframed pattern. A 0 results in a search for a framed pattern (T1 and CEPT). 4-- DPTRN0-- Detector Pattern Select. These 4 bits select which random pattern is to be transmitted. 7 DPTRN3 Description Bits Generator Standard 7654 Polynomial -- MARK (all ones) (AIS) 0000 -- -17+x-20 QRSS (220 - 1 with zero 0001 1+x O.151 suppression) 0010 25 - 1 -- 1+x-3+x-5 6 - 1) 0011 -- 63 (2 1+x-1+x-6 0100 O.153 511 (29 - 1) 1+x-5+x-9 0101 -- 511 (29 - 1) reversed 1+x-4+x-9 11 - 1) 0110 O.152 2047 (2 1+x-9+x-11 0111 -- 2047 (211 - 1) reversed 1+x-2+x-11 15 - 1 1000 O.151 2 1+x-14+x-15 1001 O.153 220 - 1 1+x-3+x-20 20 - 1 1010 CB113/CB114 2 1+x-17+x-20 1011 O.151 223 - 1 1+x-18+x-23 1100 -- 1:1 (alternating) --
* To generate/detect test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture (continued)
Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) These registers program the transmit signaling registers for the DS1 and CEPT mode. The default value of these registers is 00 (hex). Table 180. Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) ((6E0--6F7); (CE0--CF7)) Transmit Signal Registers DS1 Transmit Signaling Registers (0--23) ESF Format: Voice Channel with 16-State Signaling SLC-96: 9-State Signaling (depending on the setting in register FRM_PR43) Voice Channel with 4-State Signaling Voice Channel with 2-State Signaling Data Channel (no signaling) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P X G 0 F 0 X X D D C C B B A A
X X X
0 1 1
1 1 0
X X X
X X X
X X X
B A X
A A X
Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) Table 181. Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) ((6E0--6FF); (CE0--CFF)) Transmit Signal Registers FRM_TSR1--FRM_TSR15 FRM_TSR17--FRM_TSR31 Bit 7 P P Bit 6--5 X X Bit 4* E[1:15] E[17:31] Bit 3 D[1:15] D[17:31] Bit 2 C[1:15] C[17:31] Bit 1 B[1:15] B[17:31] Bit 0 A[1:15] A[17:31]
* In PCS0 or PCS1 signaling mode, this bit is undefined.
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Preliminary Data Sheet October 2000
FDL Register Architecture
REGBANK4 and REGBANK7 contain the status and programmable control registers for the facility data link channels FDL1 and FDL2, respectively. The base address for REGBANK4 is 800 (hex) and for REGBANK7 is E00 (hex). Within these register banks, the bit map is identical for both FDL1 and FDL2. The register bank architecture for FDL1 and FDL2 is shown in Table 184. The register bank consists of 8-bit registers classified as either (programmable) parameter registers or status registers. Default values are shown in parentheses. Table 182. FDL Register Set (800--80E); (E00--E0E)
FDL Register [Address (hex)] FDL_PR0[800;E00] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FRANSIT3 FRANSIT2 FRANSIT1 FRANSIT0 Reserved Reserved FLAGS FDINT (1) (0) (1) (0) (0) (0) (0) (0) FDL_PR1[801;E01] FTPRM FRPF FTR FRR FTE FRE FLLB FRLB (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR2[802;E02] FTBCRC FRIIE FROVIE FREOFIE FRFIE FTUNDIE FTEIE FTDIE (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR3[803;E03] FTFC FTABT FTIL5 FTIL4 FTIL3 FTIL2 FTIL1 FTIL0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR4[804;E04] FTD7 FTD6 FTD5 FTD4 FTD3 FTD2 FTD1 FTD0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR5[805;E05] FTIC7 FTIC6 FTIC5 FTIC4 FTIC3 FTIC2 FTIC1 FTIC0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR6[806;E06] FRANSIE AFDLBPM FRIL5 FRIL4 FRIL3 FRIL2 FRIL1 FRIL0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR8[808;E08] FRMC7 FRMC6 FRMC5 FRMC4 FRMC3 FRMC2 FRMC1 FRMC0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR9[809;E09] Reserved FTM FMATCH FALOCT FMSTAT FOCTOF2 FOCTOF1 FOCTOF0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_PR10[80A;E0A] FTANSI Reserved FTANSI5 FTANSI4 FTANSI3 FTANSI2 FTANSI1 FTANSI0 (0) (0) (0) (0) (0) (0) (0) (0) FDL_SR0[80B;E0B] FRANSI FRIDL FROUERUN FREOF FRF FTUNDABT FTEM FTDONE FDL_SR1[80C;E0C] FTED FTQS6 FTQS5 FTQS4 FTQS3 FTQS2 FTQS1 FTQS0 FDL_SR2[80D;E0D] FREOF FRQS6 FRQS5 FRQS4 FRQS3 FRQS2 FRQS1 FRQS0 FDL_SR3[80E;E0E] 0 0 X5 X4 X3 X2 X1 X0 FDL_SR4[807;E0F] FRD7 FRD6 FRD5 FRD4 FRD3 FRD2 FRD1 FRD0
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
FDL Parameter/Control Registers (800--80E; E00--E0E)
These registers define the mode configuration of each framer unit. These registers are initially set to a default value upon a hardware reset. These registers are all read/write registers. Default states of all bits in this register group are also indicated in the parameter/control register map. Table 183. FDL Configuration Control Register (FDL_PR0) (800; E00) Bit 0 Symbol Description
1
2--3 4--7
Dynamic Interrupt. FDINT = 0 causes multiple occurrences of the same event to generFDINT ate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0. FDINT = 1 causes multiple interrupts to be generated. This bit should normally be set to 0. Flags. FLAGS = 0 forces the transmission of the idle pattern (11111111) in the absence FLAGS of transmit FDL information. FLAGS = 1 forces the transmission of the flag pattern (01111110) in the absence of transmit FDL information. This bit resets to 0. Reserved. Write to 0. -- FRANSIT0-- Receive ANSI Bit Code Threshold. These bits define the number of ESF ANSI bit FRANSIT3 codes needed for indicating a valid code. The default is ten (1010 (binary))*.
* The FRANSIT bits (FDL_PR0 bits 4--7) must be changed only following an FDL reset or when the FDL is idle.
Table 184. FDL Control Register (FDL_PR1) (801; E01) Bit 0 1 Symbol FRLB FLLB Description Remote Loopback. FRLB = 1 loops the received facility data back to the transmit facility data interface. This bit resets to 0. Local Loopback. FLLB = 1 loops transmit facility data back to the receive facility data link interface. The receive facility data link information from the framer interface is ignored. This bit resets to 0. FDL Receiver Enable. FRE = 1 activates the FDL receiver. FRE = 0 forces the FDL receiver into an inactive state. This bit resets to 0. FDL Transmitter Enable. FTE = 1 activates the FDL transmitter. FTE = 0 forces the FDL transmitter into an inactive state. This bit resets to 0. FDL Receiver Reset. FRR = 1 generates an internal pulse that resets the FDL receiver. The FDL receiver FIFO and related circuitry are cleared. The FREOF, FRF, FRIDL, and OVERRUN interrupts are cleared. This bit resets to 0. FDL Transmitter Reset. FTR = 1 generates an internal pulse that resets the FDL transmitter. The FDL transmit FIFO and related circuitry are cleared. The FTUNDABT bit is cleared, and the FTEM interrupt is set; the FTDONE bit is forced to 0 in the HDLC mode and forced to 1 in the transparent mode. This bit resets to 0. FDL Receive PRM Frames. FRPF = 1 allows the receive FDL unit to write the entire receive performance report message including the frame header and CRC data into the receive FDL FIFO. This bit resets to 0. Transmit PRM Enable. When this bit is set, the receive framer will write into the transmit FDL FIFO its performance report message data. The current second of this data is stored in the receive framer's status registers. The receive framer's PRM is transmitted once per second. The PRM is followed by either idles or flags transmitted after the PRM. When this bit is 0, the transmit FDL expects data from the microprocessor interface.
2 3 4
FRE FTE FRR
5
FTR
6
FRPF
7
FTPRM
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FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 185. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) Bit 0 Symbol FTDIE Description FDL Transmit-Done Interrupt Enable. When this interrupt enable bit is set, an INTERRUPT pin transition is generated after the last bit of the closing flag or abort sequence is sent. In the transparent mode (register FDL_PR9 bit 6 = 1), an INTERRUPT pin transition is generated when the transmit FIFO is completely empty. FTDIE is cleared upon reset. FDL Transmitter-Empty Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the transmit FIFO has reached the programmed empty level (see register FDL_PR3). FTEIE is cleared upon reset. FDL Transmit Underrun Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the transmit FIFO has underrun. FTUNDIE is cleared upon reset and is not used in the transparent mode. FDL Receiver-Full Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receive FIFO has reached the programmed full level (see register FDL_PR6). FRFIE is cleared upon reset. FDL Receive End-of-Frame Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when an end-of-frame is detected by the FDL receiver. FREOFIE is cleared upon reset and is not used in the transparent mode. FDL Receiver Overrun Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receive FIFO overruns. FROVIE is cleared upon reset. FDL Receiver Idle-Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receiver enters the idle state. FRIIR is cleared upon reset and is not used in the transparent mode. FDL Transmit Bad CRC. Setting this bit to 1 forces bad CRCs to be sent on all transmitted frames (for test purposes) until the FTBCRC bit is cleared to 0.
1
FTEIE
2
FTUNDIE
3
FRFIE
4
FREOFIE
5
FROVIE
6
FRIIE
7
FTBCRC
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 186. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03) Bit 0--5 Symbol Description
61
71
FTIL0--FTIL5 FDL Transmitter Interrupt Level. These bits specify the minimum number of empty positions in the transmit FIFO which triggers a transmitter-empty (FTEM) interrupt. Encoding is in binary; bit 0 is the least significant bit. A code of 001010 will generate an interrupt when the transmit FIFO has ten or more empty locations. The code 000000 generates an interrupt when the transmit FIFO is empty. The number of empty transmit FIFO locations is obtained by reading the transmit FDL status register FDL_SR1. FDL Transmitter Abort. FTABT = 1 forces the transmit FDL unit to abort the frame at the FTABT last user data byte waiting for transmission. When the transmitter reads the byte tagged with FTABT, the abort sequence (01111111) is transmitted in its place. A full byte is guaranteed to be transmitted. Once set for a specific data byte, the internal FTABT status cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously written FTABT. The last value written to FTABT is available for reading. FDL Transmitter Frame Complete. FTFC = 1 forces the transmit FDL unit to terminate FTFC the frame normally after the last user data byte is written to the transmit FIFO. The CRC sequence and a closing flag are appended. FTFC should be set to 1 within 1 ms of writing the last byte of the frame in the transmit FIFO. When the transmit FIFO is empty, writing two data bytes to the FIFO before setting FTCF provides a minimum of 1 ms to write FTFC = 1. Once set for a specific data byte, the internal FTFC status bit cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC. The last value written to FTFC is available for reading.
1. Do not set FTABT = 1 and FTFC = 1 at the same time.
Table 187. FDL Transmitter FIFO Register (FDL_PR4) (804; E04) Bit 0--7 Symbol Description
FTD0--FTD7 FDL Transmit Data. The user data to be transmitted via the FDL block are loaded through this register.
Table 188. FDL Transmitter Idle Character Register (FDL_PR5) (805; E05) Bit 0--7 Symbol FTIC0-- FTIC7 Description FDL Transmitter Idle Character. This character is used only in transparent mode (register FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1, the FDL transmit unit sends this character whenever the transmit FIFO is empty. The default is to send the ones idle character, but any character can be programmed by the user.
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FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 189. FDL Receiver Interrupt Level Control Register (FDL_PR6) (806; E06) Bit 0--5 Symbol Description
6 7
FRIL0--FRIL5 FDL Receive Interrupt Level. Bit 0--bit 5 define receiver FIFO full threshold value that will generate the corresponding FRF interrupt. FRIL = 000000 forces the receive FDL FIFO to generate an interrupt when the receive FIFO is completely full. FRIL = 001111 will force the receive FDL FIFO to generate an interrupt when the receive FIFO contains 15 or more bytes. Reserved. Write to 0. -- FDL Receiver ANSI Bit Codes Interrupt Enable. If this bit is set to 1, an interrupt pin FRANSIE condition is generated whenever a valid ANSI code is received.
Table 190. FDL Register FDL_PR7 Bit 0--7 Symbol -- Reserved. Description
Table 191. FDL Receiver Match Character Register (FDL_PR8) (808; E08) Bit 0--7 Symbol FRMC0-- FRMC7 Description Receiver FDL Match Character. This character is used only in transparent mode (register FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1, the receive FDL unit searches the incoming bit stream for the receiver match character. Data is loaded into the receive FIFO only after this character has been identified. The byte identified as matching the receiver match character is the first byte loaded into the receive FIFO. The default is to search for a flag, but any character can be programmed by the user. The search for the receiver match character can be in a sliding window fashion (register FDL_PR9 bit 4 = 0) or only on byte boundaries (register FDL_PR9 bit 4 = 1).
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 192. FDL Transparent Control Register (FDL_PR9) (809; E09) Bit 0--2 Symbol FOCTOF0-- FOCTOF2 FMSTAT Description FDL Octet Offset (Read Only). These bits record the offset relative to the octet boundary when the receive character was matched. The FOCTOF bits are valid when register FDL_PR9 bit 3 (FMSTAT) is set to 1. A value of 111 (binary) indicates byte alignment. Match Status (Read Only). When this bit is set to 1 by the receive FDL unit, the receiver match character has been recognized. The octet offset status bits (FDL_PR9 bit[2:0]) indicates the offset relative to the octet boundary* at which the receive character was matched. If no match is being performed (register FDL_PR9 bit 5 = 0), the FMSTAT bit is set to 1 automatically when the first byte is received, and the octet offset status bits (register FDL_PR9 bit 0--bit 2) are set to 111 (binary). Frame-Sync Align. When this bit is set to 1, the receive FDL unit searches for the receive match character (FDL-PR8) only on an octet boundary. When this bit is 0, the receive FDL unit searches for the receive match character in a sliding window fashion. Pattern Match. FMATCH affects both the transmitter and receiver. When this bit is set to 1, the FDL does not load data into the receive FIFO until the receive match character programmed in register FDL_PR8 has been detected. The search for the receive match character is in a sliding window fashion if register FDL_PR9 bit 4 is 0, or only on octet boundaries if register FDL_PR9 bit 4 is set to 1. When this bit is 0, the receive FDL unit loads the matched byte and all subsequent data directly into the receive FIFO. On the transmit side, when this bit is set to 1 the transmitter sends the transmit idle character programmed into register FDL_PR5 when the transmit FIFO has no user data. The default idle is to transmit the HDLC ones idle character (FF hexadecimal); however, any value can be used by programming the transmit idle character register FDL_PR5. If this bit is 0, the transmitter sends ones idle characters when the transmit FIFO is empty. FDL Transparent Mode. When this bit is set to 1, the FDL unit performs no HDLC processing on incoming or outgoing data. Reserved. Write to 0.
3
4
FALOCT
5
FMATCH
6 7
FTM --
* The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).
Table 193. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (80A; E0A) Bit 0--5 6 7 Symbol FTANSI0-- FTANSI5 -- FTANSI Description FDL ESF Bit-Oriented Message Data. The transmit ESF FDL bit messages are in the form 111111110X0X1X2X3X4X50, where the order of transmission is from left to right. Reserved. Write to 0. Transmit ANSI Bit Codes. When this bit is set to 1, the FDL unit will continuously transmit the ANSI code defined using register FDL_PR10 bit 0--bit 5 as the ESF bit code messages. This bit must stay high long enough to ensure the ANSI code is sent at least 10 times.
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FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 194. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (80B; E0B) Bit 0 Symbol FTDONE Description Transmit Done. This status bit is set to 1 when transmission of the current FDL frame has been completed, either after the last bit of the closing flag or after the last bit of an abort sequence. In the transparent mode (FDL_PR9 bit 6 = 1), this status bit is set when the transmit FIFO is completely empty. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 0) is set. This status bit is cleared to 0 by a read of this register. Transmitter Empty. If this bit is set to 1, the FDL transmit FIFO is at or below the programmed depth. A hardware interrupt is generated only if the corresponding interruptenable bit (FDL_PR2 bit 1) is set. If DINT (FDL_PR0 bit 0) is 0, this status bit is cleared by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, this bit actually represents the dynamic transmit empty condition, and is cleared to 0 only when the transmit FIFO is loaded above the programmed empty level. FDL Transmit Underrun Abort. A 1 indicates that an abort was transmitted because of a transmit FIFO underrun. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 2) is set. This status bit is cleared to 0 by a read of this register. This bit must be cleared to 0 before further transmission of data is allowed. This interrupt is not generated in the transparent mode. FDL Receiver Full. This bit is set to 1 when the receive FIFO is at or above the programmed full level (FDL_PR6). A hardware interrupt is generated if the corresponding interrupt-enable bit (FDL_PR2 bit 3) is set. If FDINT (FDL_PR0 bit 0) is 0, this status bit is cleared to 0 by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, then this bit is cleared only when the receive FIFO is read (or emptied) below the programmed full level*. FDL Receive End of Frame. This bit is set to 1 when the receiver has finished receiving a frame. It becomes 1 upon reception of the last bit of the closing flag of a frame or the last bit of an abort sequence. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 4) is set. This status bit is cleared to 0 by a read of this register. This interrupt is not generated in the transparent mode. FDL Receiver Overrun. This bit is set to 1 when the receive FIFO has overrun its capacity. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*. FDL Receiver Idle. This bit is set to 1 when the FDL receiver is idle (i.e., 15 or more consecutive ones have been received). A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 6) is set. This status bit is cleared to 0 by a read of this register. This interrupt is not generated in the transparent mode. FDL Receive ANSI Bit Codes. This bit is set to 1 when the FDL receiver recognizes a valid T1.403 ESF FDL bit code. The receive ANSI bit code is stored in register FDL_SR3. An interrupt is generated only if the corresponding interrupt enable of register FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.
1
FTEM
2
FTUNDABT
3
FRF
4
FREOF
5
FROVERUN
6
FRIDL
7
FRANSI
* If an FDL receive FIFO overrun occurs, as indicated by register FDL_SR0 bit 5 (FROVERUN) = 1, the FDL must be reset to restore proper operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
FDL Parameter/Control Registers (800--80E; E00--E0E) (continued)
Table 195. FDL Transmitter Status Register (FDL_SR1) (80C; E0C) Bit 0--6 7 Symbol FTQS0-- FTQS6 FTED Description FDL Transmit Queue Status. Bit 0--bit 6 indicate how many bytes can be added to the transmit FIFO*. The bits are encoded in binary where bit 0 is the least significant bit. FDL Transmitter Empty Dynamic. FTED = 1 indicates that the number of empty locations available in the transmit FIFO is greater than or equal to the value programmed in the FTIL bits (FDL_PR3).
* The count of FDL_SR1 bits 0--6 includes SF byte.
Table 196. FDL Receiver Status Register (FDL_SR2) (80D; E0D) Bit 0--6 Symbol FRQS0-- FRQS6 FEOF Description FDL Receive Queue Status. Bit 0--bit 6 indicate how many bytes are in the receive FIFO, including the first status of Frame (SF) byte. The bits are encoded in binary where bit 0 is the least significant bit*. FDL End of Frame. When FEOF = 1, the receive queue status indicates the number of bytes up to and including the first SF byte.
7
* Immediately following an FDL reset, the value in bit 0--bit 6 of this status register is 0. After the initial read of the FDL receive FIFO, the value in bit 0--bit 6 of this status register is the number of bytes including SF byte that may be read from the FIFO.
Received FDL ANSI Bit Codes Status Register (FDL_SR3) The 6-bit code extracted from the ANSI code 111111110X0X1X2X3X4X50 is stored in this register. Table 197. Receive ANSI FDL Status Register (FDL_SR3) (80E; E0E) B7 0 B6 0 B5 X5 B4 X4 B3 X3 B2 X2 B1 X1 B0 X0
Receive FDL FIFO Register (FDL_SR4) This FIFO stores the received FDL data. Only valid FIFO bytes indicated in register FDL_SR2 may be read. Reading nonvalid FIFO locations or reading the FIFO when it is empty will corrupt the FIFO pointer and will require an FDL reset to restore proper FDL operation. Table 198. FDL Receiver FIFO Register (FDL_SR4) (807; E07) Bit Symbol Description
0--7 FRD0--FRD7 FDL Receive Data. The user data received via the FDL block are read through this register.
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Register Maps
Global Registers
Table 199. Global Register Set
REG Clear-OnRead (COR) Read (R) Write (W) COR R/W R/W R/W R/W R R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal)
GREG0 GREG1 GREG2 GREG3 GREG4 GREG5 GREG6 GREG7
Reserved (0) Reserved (0)
FDL2INT (0) FDL2IE (0)
FRMR2INT (0) FRMR2IE (0)
LIU2INT (0) LIU2IE (0)
Reserved (0) Reserved (0) TSD2-RID1 (0) TSD1-RID2 (0) T1-R2 (0) 0 0 0
FDL1INT (0) FDL1IE (0) TID2-RID1 (0) TID1-RID2 (0) T2-R1 (0) 1 0 0
FRMR1INT (0) FRMR1IE (0) TSD1-RID1 (0) TSD2-RID2 (0) Reserved (0) 1 0 1
LIU1INT (0) LIU1IE (0) TID1-RID1 (0) TID2-RID2 (0) Reserved (0) 0 0 0
000 001 002 003 004 005 006 007
TID2-RSD1 TSD2-RSD1 TID1-RSD1 TSD1-RSD1 (0) (0) (0) (0) TID1-RSD2 TSD1-RSD2 TID2-RSD2 TSD2-RSD2 (0) (0) (0) (0) Reserved (0) 0 0 0 ALIE (0) 1 0 0 SECCTRL (0) 1 1 0 Reserved (0) 1 1 0
Line Interface Unit Parameter/Control and Status Registers
Table 200. Line Interface Unit Register Set*
LIU_REG Clear-OnRead (COR) Read (R) Write (W) COR R/W R/W R/W R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer 1 Reserved Reserved (0) Reserved (0) Reserved (1)
Framer 2 A00 A01 A02 A03 A04 A05 A06
LIU_REG0 LIU_REG1 LIU_REG2 LIU_REG3 LIU_REG4 LIU_REG5 LIU_REG6
Reserved Reserved (0) Reserved (0) Reserved (1)
Reserved Reserved (0) RESTART (0) Reserved (1) JABW0 (0) Reserved (0) Reserved (0)
Reserved Reserved (0) HIGHZ (0) LOSSD (0) PHIZALM (0) Reserved (0) Reserved (0)
LOTC LOTCIE (0) Reserved (0) DUAL (0) PRLALM (0) LOOPA (0) Reserved (0)
TDM TDMIE (0) LOSSTD (0) CODE (1) PFLALM (0) LOOPB (0) EQ2 (0,DS1) (1,CEPT)
DLOS DLOSIE (0) Reserved (0) JAT (0) RCVAIS (0) XLAIS (1) EQ1 (0,DS1) (1,CEPT)
ALOS ALOSIE (0) Reserved (0) JAR (0) ALTIMER (0) PWRDN (0) EQ0 (0)
400 401 402 403 404 405 406
Reserved (0) Reserved (0) Reserved (0)
Reserved (0) Reserved (0) Reserved (0)
* The logic value in parentheses below each bit definition is the default state upon completion of hardware reset. These bits must be written to 1.
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Maps (continued)
Framer Parameter/Control Registers (Read-Write)
Table 201. Framer Unit Status Register Map
Framer Status Clear-OnRead (COR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer Framer 1 2 FRM_SR0 FRM_SR1 FRM_SR2 FRM_SR3 FRM_SR4 FRM_SR5 FRM_SR6 FRM_SR7 FRM_SR8 FRM_SR9 FRM_SR10 FRM_SR11 FRM_SR12 FRM_SR13 FRM_SR14 FRM_SR15 FRM_SR16 FRM_SR17 FRM_SR18 FRM_SR19 FRM_SR20 FRM_SR21 FRM_SR22 FRM_SR23 FRM_SR24 FRM_SR25 FRM_SR26 FRM_SR27 FRM_SR28 FRM_SR29 FRM_SR30 FRM_SR31 FRM_SR32 FRM_SR33 FRM_SR34 FRM_SR35 COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR S96SR AIS RSa6 = F SLIPU FDL-LLBOFF TSaSR ETREUAS NTREUAS RQUASI BPV15 BPV7 FE15 FE7 CEC15 CEC7 REC15 REC7 CNT15 CNT7 ENT15 ENT7 ETES15 ETES7 ETBES15 ETBES7 ETSES15 ETSES7 ETUS15 ETUS7 ETREES15 ETREES7 ETREBES15 ETREBES7 ETRESES15 ETRESES7 ETREUS15 ETREUS7 0 AUXP RSa6 = E SLIPO FDL-LLBON RSaSR ETRESES NTRESES RPSEUDO BPV14 BPV6 FE14 FE6 CEC14 CEC6 REC14 REC6 CNT14 CNT6 ENT14 ENT6 ETES14 ETES6 ETBES14 ETBES6 ETSES14 ETSES6 ETUS14 ETUS6 ETREES14 ETREES6 ETREBES14 ETREBES6 ETRESES14 ETRESES6 ETREUS14 ETREUS6 RSSFE RTS16AIS RSa6 = C LCRCATMX FDL-PLBOFF ETREBES NTREBES PTRNBER BPV13 BPV5 FE13 FE5 CEC13 CEC5 REC13 REC5 CNT13 CNT5 ENT13 ENT5 ETES13 ETES5 ETBES13 ETBES5 ETSES13 ETSES5 ETUS13 ETUS5 ETREES13 ETREES5 ETREBES13 ETREBES5 ETRESES13 ETRESES5 ETREUS13 ETREUS5 TSSFE LBFA RSa6 = A REBIT FDL-PLBON ETREES NTREES DETECT BPV12 BPV4 FE12 FE4 CEC12 CEC4 REC12 REC4 CNT12 CNT4 ENT12 ENT4 ETES12 ETES4 ETBES12 ETBES4 ETSES12 ETSES4 ETUS12 ETUS4 ETREES12 ETREES4 ETREBES4 ETRESES4 ETREUS12 ETREUS4 ESE LFALR RSa6 = 8 ECE LLBON CMA ETUAS NTUAS NROUAS BPV11 BPV3 FE11 FE3 CEC11 CEC3 REC11 REC3 CNT11 CNT3 ENT11 ENT3 ETES11 ETES3 ETBES11 ETBES3 ETSES11 ETSES3 ETUS11 ETUS3 ETREES11 ETREES3 ETREBES3 ETRESES3 ETREUS11 ETREUS3 FAE LTSFA LTS0MFA CREBIT CRCE LLBOFF BFA ETSES NTSES NT1OUAS BPV10 BPV2 FE10 FE2 CEC10 CEC2 REC10 REC2 CNT10 CNT2 ENT10 ENT2 ETES10 ETES2 ETBES10 ETBES2 ETSES10 ETSES2 ETUS10 ETUS2 ETREES10 ETREES2 ETREBES2 ETRESES2 ETREUS10 ETREUS2 RAC LSFA LTS16MFA RJYA RTS16MFA FBE SSFA ETBES NTBES EROUAS BPV9 BPV1 FE9 FE1 CEC9 CEC1 REC9 REC1 CNT9 CNT1 ENT9 ENT1 ETES9 ETES1 ETBES9 ETBES1 ETSES9 ETSES1 ETUS9 ETUS1 ETREES9 ETREES1 ETREBES9 ETREBES1 ETRESES9 ETRESES1 ETREUS9 ETREUS1 FAC LFA RFA LFV NFA ETES NTES OUAS BPV8 BPV0 FE8 FE0 CEC8 CEC0 REC8 REC0 CNT8 CNT0 ENT8 ENT0 ETES8 ETES0 ETBES8 ETBES0 ETSES8 ETSES0 ETUS8 ETUS0 ETREES8 ETREES0 ETREBES8 ETREBES0 ETRESES8 ETRESES0 ETREUS8 ETREUS0 600 601 602 603 604 605 606 607 608 609 60A 60B 60C 60D 60E 60F 610 611 612 613 614 615 616 617 618 619 61A 61B 61C 61D 61E 61F 620 621 622 623 C00 C01 C02 C03 C04 C05 C06 C07 C08 C09 C0A C0B C0C C0D C0E C0F C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C1A C1B C1C C1D C1E C1F C20 C21 C22 C23
ETREBES12 ETREBES11 ETREBES10 ETRESES12 ETRESES11 ETRESES10
* Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.
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Preliminary Data Sheet October 2000
Register Maps (continued)
Table 201. Framer Unit Status Register Map (continued)
Framer Status Clear-OnRead (COR) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer Framer 1 2 FRM_SR36 FRM_SR37 FRM_SR38 FRM_SR39 FRM_SR40 FRM_SR41 FRM_SR42 FRM_SR43 FRM_SR44 FRM_SR45 FRM_SR46 FRM_SR47 FRM_SR48 FRM_SR49 FRM_SR50 FRM_SR51 FRM_SR52 FRM_SR53 FRM_SR54* FRM_SR55 FRM_SR56
*
COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR
NTES15 NTES7 NTBES15 NTBES7 NTSES15 NTSES7 NTUS15 NTUS7 NTREES15 NTREES7 NTREBES15 NTREBES7 NTRESES15 NTRESES7 NTREUS15 NTREUS7 NFB1 [FI5E] 0 0 [Sa4-1] 0 [Sa4-17] RC1 [Sa5-1] RC9 [Sa5-17] RM3 [Sa6-1] 0 [Sa6-17] 0 [Sa7-1] 0 [Sa7-17] G3 [Sa8-1] FE [Sa8-17]
NTES14 NTES6 NTBES14 NTBES6 NTSES14 NTSES6 NTUS14 NTUS6 NTREES14 NTREES6 NTREBES14 NTREBES6 NTRESES14 NTRESES6 NTREUS14 NTREUS6 FBI [FI3E] 0 0 [Sa4-3] 0 [Sa4-19] RC2 [Sa5-3] RC10 [Sa5-19] RA1 [Sa6-3] 0 [Sa6-19] 0 [Sa7-3] 0 [Sa7-19] LV [Sa8-3] SE [Sa8-19]
NTES13 NTES5 NTBES13 NTBES5 NTSES13 NTSES5 NTUS13 NTUS5 NTREES13 NTREES5 NTREBES13 NTREBES5 NTRESES13 NTRESES5 NTREUS13 NTREUS5 A bit 0 R-0 [Sa4-5] R-0 [Sa4-21] RC3 [Sa5-5] RC11 [Sa5-21] RA2 [Sa6-5] 0 [Sa6-21] 0 [Sa7-5] 0 [Sa7-21] G4 [Sa8-5] LB [Sa8-21]
NTES12 NTES4 NTBES12 NTBES4 NTSES12 NTSES4 NTUS12 NTUS4 NTREES12 NTREES4 NTREBES12 NTREBES4 NTRESES12 NTRESES4 NTREUS12 NTREUS4 Sa4 0 R-0 [Sa4-7] R-0 [Sa4-23] RC4 [Sa5-7] RSPB1 = 0 [Sa5-23] RS1 [Sa6-7] 0 [Sa6-23] 0 [Sa7-7] 0 [Sa7-23] U1 [Sa8-7] G1 [Sa8-23]
NTES11 NTES3 NTBES11 NTBES3 NTSES11 NTSES3 NTUS11 NTUS3 NTREES11 NTREES3 NTREBES11 NTREBES3 NTRESES11 NTRESES3 NTREUS11 NTREUS3 Sa5 0 R-0 [Sa4-9] R-0 [Sa4-25] RC5 [Sa5-9] RSPB2 = 1 [Sa5-25] RS2 [Sa6-9] 0 [Sa6-25] 0 [Sa7-9] 0 [Sa7-25] U2 [Sa8-9] R [Sa8-25]
NTES10 NTES2 NTBES10 NTBES2 NTSES10 NTSES2 NTUS10 NTUS2 NTREES10 NTREES2 NTREBES10 NTREBES2 NTRESES10 NTRESES2 NTREUS10 NTREUS2 Sa6 RX2 R-1 [Sa4-11] R-1 [Sa4-27] RC6 [Sa5-11] RSPB3 = 0 [Sa5-27] RS3 [Sa6-11] 0 [Sa6-27] 0 [Sa7-11] 0 [Sa7-27] G5 [Sa8-11] G2 [Sa8-27]
NTES9 NTES1 NTBES9 NTBES1 NTSES9 NTSES1 NTUS9 NTUS1 NTREES9 NTREES1 NTREBES9 NTREBES1 NTRESES9 NTRESES1 NTREUS9 NTREUS1 Sa7 RX1 R-1 [Sa4-13] R-1 [Sa4-29] RC7 [Sa5-13] RM1 [Sa5-29] RS4 [Sa613] 0 [Sa6-29] 0 [Sa7-13] 0 [Sa7-29] SL [Sa8-13] Nm [Sa8-29]
NTES8 NTES0 NTBES8 NTBES0 NTSES8 NTSES0 NTUS8 NTUS0 NTREES8 NTREES0 NTREBES8 NTREBES0 NTRESES8 NTRESES0 NTREUS8 NTREUS0 Sa8 RX0 R-1 [Sa4-15] R-1 [Sa4-31] RC8 [Sa5-15] RM2 [Sa5-31] RSPB4 = 1 [Sa6-15] 0 [Sa6-31] 0 [Sa7-15] 0 [Sa7-31] G6 [Sa8-15] Nl [Sa8-31]
624 625 626 627 628 629 62A 62B 62C 62D 62E 62F 630 631 632 633 634 635 636 637 638 639 63A 63B 63C 63D 63E 63F
C24 C25 C26 C27 C28 C29 C2A C2B C2C C2D C2E C2F C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C3A C3B C3C C3D C3E C3F
*
FRM_SR57* FRM_SR58
*
FRM_SR59* FRM_SR60
*
FRM_SR61* FRM_SR62
*
FRM_SR63*
* Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.
200
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Maps (continued)
Receive Framer Signaling Registers (Read-Only)
Table 202. Receive Signaling Registers Map
Receive Signaling Read (R) Bit 7 Bit 6* Bit 5* Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer 1 FRM_RSR0** FRM_RSR1 FRM_RSR2 FRM_RSR3 FRM_RSR4 FRM_RSR5 FRM_RSR6 FRM_RSR7 FRM_RSR8 FRM_RSR9 FRM_RSR10 FRM_RSR11 FRM_RSR12 FRM_RSR13 FRM_RSR14 FRM_RSR15 FRM_RSR16 FRM_RSR17 FRM_RSR18 FRM_RSR19 FRM_RSR20 FRM_RSR21 FRM_RSR22 FRM_RSR23 FRM_RSR24 FRM_RSR25 FRM_RSR26 FRM_RSR27 FRM_RSR28 FRM_RSR29 FRM_RSR30 FRM_RSR31
*
Framer 2 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C4A C4B C4C C4D C4E C4F C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C5A C5B C5C C5D C5E C5F
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
G_0 G_1 G_2 G_3 G_4 G_5 G_6 G_7 G_8 G_9 G_10 G_11 G_12 G_13 G_14 G_15 G_16 G_17 G_18 G_19 G_20 G_21 G_22 G_23 X X X X X X X X
F_0 F_1 F_2 F_3 F_4 F_5 F_6 F_7 F_8 F_8 F_10 F_11 F_12 F_13 F_14 F_15 F_16 F_17 F_18 F_19 F_20 F_21 F_22 F_23 X X X X X X X X
E_0 E_1 E_2 E_3 E_4 E_5 E_6 E_7 E_8 E_8 E_10 E_11 E_12 E_13 E_14 E_15 E_16 E_17 E_18 E_19 E_20 E_21 E_22 E_23 E_24 E_25 E_26 E_27 E_28 E_29 E_30 E_31
D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_8 D_10 D_11 D_12 D_13 D_14 D_15 D_16 D_17 D_18 D_19 D_20 D_21 D_22 D_23 D_24 D_25 D_26 D_27 D_28 D_29 D_30 D_31
C_0 C_1 C_2 C_3 C_4 C_5 C_6 C_7 C_8 C_8 C_10 C_11 C_12 C_13 C_14 C_15 C_16 C_17 C_18 C_19 C_20 C_21 C_22 C_23 C_24 C_25 C_26 C_27 C_28 C_29 C_30 C_31
B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_8 B_10 B_11 B_12 B_13 B_14 B_15 B_16 B_17 B_18 B_19 B_20 B_21 B_22 B_23 B_24 B_25 B_26 B_27 B_28 B_29 B_30 B_31
A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_8 A_10 A_11 A_12 A_13 A_14 A_15 A_16 A_17 A_18 A_19 A_20 A_21 A_22 A_23 A_24 A_25 A_26 A_27 A_28 A_29 A_30 A_31
640 641 642 643 644 645 646 647 648 649 64A 64B 64C 64D 64E 64F 650 651 652 653 654 655 656 657 658 659 65A 65B 65C 65D 65E 65F
In the DS1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. In the CEPT signaling modes, these bits are in the 0 state and should be ignored. In the DS1 signaling modes, these registers contain unknown data. In DS1 4-state and 2-state signaling, these bits contain unknown data. In DS1 2-state signaling, these bits contain unknown data. ** In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data. Signifies unknown data.
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Preliminary Data Sheet October 2000
Register Maps (continued)
Framer Unit Parameter Register Map
Table 203. Framer Unit Parameter Register Map
Framer Control Read (R) Write (W) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer Framer 1 2 FRM_PR0 FRM_PR1 FRM_PR2 FRM_PR3 FRM_PR4 FRM_PR5 FRM_PR6 FRM_PR7 FRM_PR8 FRM_PR9 FRM_PR10 FRM_PR11 FRM_PR12 FRM_PR13 FRM_PR14 FRM_PR15 FRM_PR16 FRM_PR17 FRM_PR18 FRM_PR19 FRM_PR20 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SLCIE (0) SR1B7IE (0) SR2B7IE (0) SR3B7IE (0) SR4B7IE (0) SR5B7IE (0) SR6B7IE (0) SR7B7IE (0) LC2 (1) CRCO7 (0) ESM1 (0) EST7 (0) SEST15 (0) SEST7 (0) 0 ETRESa6-F (0) NTSa6-C (0) 0 0 AFDPLBE (0) TICRC (0) Reserved (0) SR1B6IE (0) SR2B6IE (0) SR3B6IE (0) SR4B6IE (0) SR5B6IE (0) SR6B6IE (0) SR7B6IE (0) LC1 (1) CRCO6 (0) ESM0 (0) EST6 (0) SEST14 (0) SEST6 (0) 0 ETRESa6-E (0) 0 0 0 AFDLLBE (0) TLIC (0) RSRIE (0) SR1B5IE (0) SR2B5IE (0) SR3B5IE (0) SR4B5IE (0) SR5B5IE (0) SR6B5IE (0) SR7B5IE (0) LC0 (0) CRCO5 (0) Reserved (0) EST5 (0) SEST13 (0) SEST5 (0) 0 ETRESa6-8 (0) NTSa6-8 (0) 0 0 Reserved (0) TLLBOFF (0) TSRIE (0) SR1B4IE (0) SR2B4IE (0) SR3B4IE (0) SR4B4IE (0) SR5B4IE (0) SR6B4IE (0) SR7B4IE (0) FMODE4 (0) CRCO4 (0) Reserved (0) EST4 (0) SEST12 (0) SEST4 (0) 0 ETRERFA (0) 0 NTRERFA (0) 0 ALLBE (0) TLLBON (0) SR567IE (0) SR1B3IE (0) SR2B3IE (0) SR3B3IE (0) SR4B3IE (0) SR5B3IE (0) SR6B3IE (0) SR7B3IE (0) FMODE3 (0) CRCO3 (0) CNUCLBEN (0) EST3 (0) SEST11 (0) SEST3 (0) ETSLIP (0) ETRESLIP (0) NTSLIP (0) NTRESLIP (0) NTRESa6-C (0) TSAIS (0) TQRS (0) SR34IE (0) SR1B2IE (0) SR2B2IE (0) SR3B2IE (0) SR4B2IE (0) SR5B2IE (0) SR6B2IE (0) SR7B2IE (0) FMODE2 (0) CRCO2 (0) FEREN (0) EST2 (0) SEST10 (0) SEST2 (0) ETAIS (0) ETREAIS (0) NTAIS (0) NTREAIS (0) SR2IE (0) SR1B1IE (0) SR2B1IE (0) SR3B1IE (0) SR4B1IE (0) SR5B1IE (0) SR6B1IE (0) SR7B1IE (0) FMODE1 (0) CRCO1 (0) AISM (0) EST1 (0) SEST9 (0) SEST1 (0) ETLMFA (0) ETRELMFA (0) NTLMFA (0) NTRELMFA (0) SR1IE (0) SR1B0IE (0) SR2B0IE (0) SR3B0IE (0) SR4B0IE (0) SR5B0IE (0) SR6B0IE (0) SR7B0IE (0) FMODE0 (0) CRCO0 (0) SSa6M (0) EST0 (0) SEST8 (0) SEST0 (0) ETLFA (0) ETRELFA (0) NTLFA (0) NTRELFA (0) 660 661 662 663 664 665 666 667 668 669 66A 66B 66C 66D 66E 66F 670 671 672 673 674 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C6A C6B C6C C6D C6E C6F C70 C71 C72 C73 C74
NTRESa6-F NTRESa6-E NTRESa6-8 (0) (0) (0) Reserved (0) TPRS (0) ASAISTMX (0) TUFAUXP (0) ASAIS (0) TUFAIS (0)
202
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Maps (continued)
Table 203. Framer Unit Parameter Register Map (continued)
Framer Control Read (R) Write (W) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer Framer 1 2 FRM_PR21 FRM_PR22 FRM_PR23 FRM_PR24 FRM_PR25 FRM_PR26 R/W R/W R/W R/W R/W R/W TC/R = 1 (0) TLIC7 (0) SSTSC7 (0) LBC2 (0) Reserved (0) Reserved (0) TRFA (0) 0 SaS7 (0) TDNF (0) 0 Sa4-1 0 Sa4-17 XC1 Sa5-1 XC9 Sa5-17 XM3 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Reserved (0) TFDLC (0) TLIC6 (1) SSTSC6 (1) LBC1 (0) SLBC1 (0) Reserved (0) TJRFA (0) 0 SaS6 (0) Reserved (0) 0 Sa4-3 0 Sa4-19 XC2 Sa5-3 XC10 Sa5-19 XA1 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 TLTS16AIS (0) TFDLSAIS (0) TLIC5 (1) SSTSC5 (1) LBC0 (0) SLBC0 (0) SYSFSM (0) AARSa6_C (0) ATERTX (0) SaS5 (0) Reserved (0) X-0 Sa4-5 X-0 Sa4-21 XC3 Sa5-5 XC11 Sa5-21 XA2 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 TLTS16RMFA (0) TFDLLAIS (0) TLIC4 (1) SSTSC4 (1) TSLBA4 (0) STSLBA4 (0) TFM2 (0) AARSa6_8 (0) ATELTS0MFA (0) TSa8 (0) TESa8 (0) X-0 Sa4-7 X-0 Sa4-23 XC4 Sa5-7 XSPB1 = 0 Sa5-23 XS1 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 ALTTS16RMFA (0) Reserved (0) TLIC3 (1) SSTSC3 (1) TSLBA3 (0) STSLBA3 (0) TFM1 (0) ATMX (0) ATECRCE (0) TSa7 (0) TESa7 (0) X-0 Sa4-9 X-0 Sa4-25 XC5 Sa5-9 XSPB2 = 1 Sa5-25 XS2 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 XS (0) Reserved (0) TLIC2 (1) SSTSC2 (1) TSLBA2 (0) STSLBA2 (0) FRFRM (0) AAB0LMFA (0) TSiNF (0) TSa6 (0) TESa6 (0) X-1 Sa4-11 X-1 Sa4-27 XC6 Sa5-11 XSPB3 = 0 Sa5-27 XS3 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 TTS16X2 (0) Reserved (0) TLIC1 (1) SSTSC1 (1) TSLBA1 (0) STSLBA1 (0) SWRESTART (0) AAB16LMFA (0) TSiF (0) TSa5 (0) TESa5 (0) X-1 Sa4-13 X-1 Sa4-29 XC7 Sa5-13 XM1 Sa5-29 XS4 Sa613 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 TTS16X1 (0) Reserved (0) TLIC0 (1) SSTSC0 (1) TSLBA0 (0) STSLBA0 (0) SWRESET (0) ARLFA (0) SIS, T1E (0) TSa4 (0) TESa4 (0) X-1 Sa4-15 X-1 Sa4-31 XC8 Sa5-15 XM2 Sa5-31 XSPB4 = 1 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31 TTS16X0 (0) 675 676 677 678 679 67A C75 C76 C77 C78 C79 C7A
FRM_PR27 FRM_PR28 FRM_PR29 FRM_PR30 FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36 FRM_PR37 FRM_PR38 FRM_PR39 FRM_PR40 FRM_PR41
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
67B 67C 67D 67E 67F 680 681 682 683 684 685 686 687 688 689
C7B C7C C7D C7E C7F C80 C81 C82 C83 C84 C85 C86 C87 C88 C89
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Preliminary Data Sheet October 2000
Register Maps (continued)
Table 203. Framer Unit Parameter Register Map (continued)
Framer Control Read (R) Write (W) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer Framer 1 2 FRM_PR42 FRM_PR43 R/W R/W FEX7 (0) Reserved (0) TCSS (0) HWYEN (0) RFE (0) Reserved (0) Reserved (0) TTSE31 (0) TTSE23 (0) TTSE15 (0) TTSE7 (0) RTSE31 (0) RTSE23 (0) RTSE15 (0) RTSE7 (0) THS31 (0) THS23 (0) THS15 (0) THS7 (0) RHS31 (0) RHS23 (0) RHS15 (0) RHS7 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN3 (0) DPTRN3 (0) FEX6 (0) Reserved (0) ASTSAIS (0) Reserved (0) ROFF2 (0) TCE (0) RCE (0) TTSE30 (0) TTSE22 (0) TTSE14 (0) TTSE6 (0) RTSE30 (0) RTSE22 (0) RTSE14 (0) RTSE6 (0) THS30 (0) THS22 (0) THS14 (0) THS6 (0) RHS30 (0) RHS22 (0) RHS14 (0) RHS6 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN2 (0) DPTRN2 (0) FEX5 (0) Reserved (0) TSR-ASM (0) Reserved (0) ROFF1 (0) TBYOFF5 (0) RBYOFF5 (0) TTSE29 (0) TTSE21 (0) TTSE13 (0) TTSE5 (0) RTSE29 (0) RTSE21 (0) RTSE13 (0) RTSE5 (0) THS29 (0) THS21 (0) THS13 (0) THS5 (0) RHS29 (0) RHS21 (0) RHS13 (0) RHS5 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN1 (0) DPTRN1 (0) FEX4 (0) Reserved (0) MOS (0) CHIMM (0) ROFF0 (0) TBYOFF4 (0) RBYOFF4 (0) TTSE28 (0) TTSE20 (0) TTSE12 (0) TTSE4 (0) RTSE28 (0) RTSE20 (0) RTSE12 (0) RTSE4 (0) THS28 (0) THS20 (0) THS12 (0) THS4 (0) RHS28 (0) RHS20 (0) RHS12 (0) RHS4 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN0 (0) DPTRN0 (0) FEX3 (0) SSC (0) RSI (0) CDRS1 (0) TFE (0) TBYOFF3 (0) RBYOFF3 (0) TTSE27 (0) TTSE19 (0) TTSE11 (0) TTSE3 (0) RTSE27 (0) RTSE19 (0) RTSE11 (0) RTSE3 (0) THS27 (0) THS19 (0) THS11 (0) THS3 (0) RHS27 (0) RHS19 (0) RHS11 (0) RHS3 (0) Reserved (0) Reserved (0) Reserved Reserved GFRMSEL (0) DUFTP (0) FEX2 (0) STS2 [SaFDL2] (0) ASM (0) CDRS0 (0) TOFF2 (0) TBYOFF2 (0) RBYOFF2 (0) TTSE26 (0) TTSE18 (0) TTSE10 (0) TTSE2 (0) RTSE26 (0) RTSE18 (0) RTSE10 (0) RTSE2 (0) THS26 (0) THS18 (0) THS10 (0) THS2 (0) RHS26 (0) RHS18 (0) RHS10 (0) RHS2 (0) Reserved (0) Reserved (0) Reserved Reserved GBLKSEL (0) DBLKSEL (0) FEX1 (0) STS1 [SaFDL1] (0) STOMP (0) CMS (0) TOFF1 (0) TBYOFF1 (0) RBYOFF1 (0) TTSE25 (0) TTSE17 (0) TTSE9 (0) TTSE1 (0) RTSE25 (0) RTSE17 (0) RTSE9 (0) RTSE1 (0) THS25 (0) THS17 (0) THS9 (0) THS1 (0) RHS25 (0) RHS17 (0) RHS9 (0) RHS1 (0) TCHIDTS (0) RCHIDTS (0) Reserved Reserved TPEI (0) reserved (0) FEX0 (0) STS0 [SaFDL0] (1) TSIG (0) HFLF (0) TOFF0 (0) TBYOFF0 (0) RBYOFF0 (0) TTSE24 (0) TTSE16 (0) TTSE8 (0) TTSE0 (0) RTSE24 (0) RTSE16 (0) RTSE8 (0) RTSE0 (0) THS24 (0) THS16 (0) THS8 (0) THS0 (0) RHS24 (0) RHS16 (0) RHS8 (0) RHS0 (0) TBYOFF6 (0) RBYOFF6 (0) Reserved Reserved ITD (0) IRD (0) 68A 68B C8A C8B
FRM_PR44 FRM_PR45 FRM_PR46 FRM_PR47 FRM_PR48 FRM_PR49 FRM_PR50 FRM_PR51 FRM_PR52 FRM_PR53 FRM_PR54 FRM_PR55 FRM_PR56 FRM_PR57 FRM_PR58 FRM_PR59 FRM_PR60 FRM_PR61 FRM_PR62 FRM_PR63 FRM_PR64 FRM_PR65 FRM_PR66 FRM_PR67 FRM_PR68 FRM_PR69 FRM_PR70
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- R/W R/W
68C 68D 68E 68F 690 691 692 693 694 695 696 697 698 699 69A 69B 69C 69D 69E 69F 6A0 6A1 6A2 6A3 6A4 6A5 6A6
C8C C8D C8E C8F C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C9A C9B C9C C9D C9E C9F CA0 CA1 CA2 CA3 CA4 CA5 CA6
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Register Maps (continued)
Transmit Signaling Registers (Read/Write)
Table 204. Transmit Signaling Registers Map
Transmit Signaling Read (R) Write (W) Bit 7 Bit 6* Bit 5* Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer 1 FRM_TSR0** FRM_TSR1 FRM_TSR2 FRM_TSR3 FRM_TSR4 FRM_TSR5 FRM_TSR6 FRM_TSR7 FRM_TSR8 FRM_TSR9 FRM_TSR10 FRM_TSR11 FRM_TSR12 FRM_TSR13 FRM_TSR14 FRM_TSR15 FRM_TSR16** FRM_TSR17 FRM_TSR18 FRM_TSR19 FRM_TSR20 FRM_TSR21 FRM_TSR22 FRM_TSR23 FRM_TSR24 FRM_TSR25
Framer 2 CE0 CE1 CE2 CE3 CE4 CE5 CE6 CE7 CE8 CE9 CEA CEB CEC CED CEE CEF CF0 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8 CF9 CFA CFB CFC CFD CFE CFF
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
G_0 G_1 G_2 G_3 G_4 G_5 G_6 G_7 G_8 G_9 G_10 G_11 G_12 G_13 G_14 G_15 G_16 G_17 G_18 G_19 G_20 G_21 G_22 G_23 X X X X X X X X
F_0 F_1 F_2 F_3 F_4 F_5 F_6 F_7 F_8 F_8 F_10 F_11 F_12 F_13 F_14 F_15 F_16 F_17 F_18 F_19 F_20 F_21 F_22 F_23 X X X X X X X X
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_8 D_10 D_11 D_12 D_13 D_14 D_15 D_16 D_17 D_18 D_19 D_20 D_21 D_22 D_23 D_24 D_25 D_26 D_27 D_28 D_29 D_30 D_31
C_0 C_1 C_2 C_3 C_4 C_5 C_6 C_7 C_8 C_8 C_10 C_11 C_12 C_13 C_14 C_15 C_16 C_17 C_18 C_19 C_20 C_21 C_22 C_23 C_24 C_25 C_26 C_27 C_28 C_29 C_30 C_31
B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_8 B_10 B_11 B_12 B_13 B_14 B_15 B_16 B_17 B_18 B_19 B_20 B_21 B_22 B_23 B_24 B_25 B_26 B_27 B_28 B_29 B_30 B_31
A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_8 A_10 A_11 A_12 A_13 A_14 A_15 A_16 A_17 A_18 A_19 A_20 A_21 A_22 A_23 A_24 A_25 A_26 A_27 A_28 A_29 A_30 A_31
6E0 6E1 6E2 6E3 6E4 6E5 6E6 6E7 6E8 6E9 6EA 6EB 6EC 6ED 6EE 6EF 6F0 6F1 6F2 6F3 6F4 6F5 6F6 6F7 6F8 6F9 6FA 6FB 6FC 6FD 6FE 6FF
FRM_TSR26 FRM_TSR27 FRM_TSR28 FRM_TSR29 FRM_TSR30 FRM_TSR31 *
In the normal DS1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are copied into the received signaling registers. In the CEPT signaling modes, these bits are ignored. These bits contain unknown data. In DS1 4-state and 2-state signaling modes, these bits contain unknown data. In DS1 2-state signaling mode, these bits contain unknown data. ** In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data. In the DS1 signaling modes, these registers contain unknown data. Signifies known data.
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Preliminary Data Sheet October 2000
Register Maps (continued)
Facility Data Link Parameter/Control and Status Registers (Read-Write)
Table 205. Facility Data Link Register Map
Transmit Signaling ClearOn-Read (COR) Read (R) Write (W) R/W R/W R/W R/W R/W R/W R/W Reserved R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hexadecimal) Framer 1 FRANSIT3 FRANSIT2 FRANSIT1 FRANSIT0 Reserved Reserved (1) (0) (1) (0) (0) (0) FTPRM (0) FTBCRC (0) FTFC (0) FTD7 (0) FTIC7 (0) FRANSIE (0) Reserved FRMC7 (0) Reserved (0) FTANSI (0) FRANSI FTED FREOF 0 FRD7 (0) FRPF (0) FRIIE (0) FTABT (0) FTD6 (0) FTIC6 (0) Reserved (0) Reserved FRMC6 (0) FTM (0) Reserved (0) FRIDL FTQS6 FRQS6 0 FRD6 (0) FTR (0) FROVIE (0) FTIL5 (0) FTD5 (0) FTIC5 (0) FRIL5 (0) Reserved FRMC5 (0) FMATCH (0) FTANSI5 (0) FROVERU N FTQS5 FRQS5 X5 FRD5 (0) FRR (0) FREOFIE (0) FTIL4 (0) FTD4 (0) FTIC4 (0) FRIL4 (0) Reserved FRMC4 (0) FALOCT (0) FTANSI4 (0) FREOF FTQS4 FRQS4 X4 FRD4 (0) FTE (0) FRFIE (0) FTIL3 (0) FTD3 (0) FTIC3 (0) FRIL3 (0) FRMC3 (0) FMSTAT (0) FTANSI3 (0) FRF FTQS3 FRQS3 X3 FRD3 (0) FRE (0) FTUNDIE (0) FTIL2 (0) FTD2 (0) FTIC2 (0) FRIL2 (0) FRMC2 (0) FLAGS (0) FLLB (0) FTEIE (0) FTIL1 (0) FTD1 (0) FTIC1 (0) FRIL1 (0) Reserved FRMC1 (0) FDINT (0) FRLB (0) FTDIE (0) FTIL0 (0) FTD0 (0) FTIC0 (0) FRIL0 (0) Reserved FRMC0 (0) 800 801 802 803 804 805 806 -- 808 809 Framer 2 E00 E01 E02 E03 E04 E05 E06 -- E08 E09
FDL_PR0 FDL_PR1 FDL_PR2 FDL_PR3 FDL_PR4 FDL_PR5 FDL_PR6 FDL_PR7 FDL_PR8 FDL_PR9
Reserved Reserved
FOCTOF2 FOCTOF FOCTOF0 (0) (0) 1 (0) FTANSI2 (0) FTUNDA BT FTQS2 FRQS2 X2 FRD2 (0) FTANSI1 (0) FTEM FTQS1 FRQS1 X1 FRD1 (0) FTANSI0 (0) FTDONE FTQS0 FRQS0 X0 FRD0 (0)
FDL_PR10 FDL_SR0 FDL_SR1 FDL_SR2 FDL_SR3 FDL_SR4
R/W COR R R R R
80A 80B 80C 80D 80E 807
E0A E0B E0C E0D E0E E07
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter VDD Supply Voltage Range Maximum Voltage (digital pins) with Respect to VDD Minimum Voltage (digital pins) with Respect to GRND Maximum Allowable Voltages (RTIP RRING) with , Respect to VDD Minimum Allowable Voltages (RTIP RRING) with , Respect to GRND Storage Temperature Range Symbol VDD -- -- -- -- Tstg Min -0.5 -- -0.3 -- -0.5 -65 Max 7 0.3 -- 0.5 -- 125 Unit V V V V V C
Operating Conditions
Parameter Power Supply Power Dissipation Ambient Temperature Symbol VDD PD TA Min 4.75 -- -40 Typ 5.0 500 -- Max 5.25 750 85 Unit V mW C
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. Table 206. ESD Threshold Voltage Device T7630 Voltage >1000 V
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Preliminary Data Sheet October 2000
Electrical Characteristics
Logic Interface Characteristics
Table 207. Logic Interface Characteristics (TA = -40 C to +85 C, VDD = 5.0 V 5%, VSS = 0) Parameter Input Voltage: Low High Input Leakage Output Voltage: Low High Input Capacitance Load Capacitance Symbol VIL VIH IL VOL VOH CI CL Test Conditions IIL = -70 A* IIH = 10 A -- IOL = -5.0 mA* IOH = 5.0 mA -- -- Min 0 2.1 -- 0 VDD - 0.5 -- -- Max 0.8 VDD 10 0.4 VDD 3.0 50 Unit V V A V V pF pF
* Sinking. Sourcing. 100 pF allowed for AD[7:0] (pins 86 to 79) and A[11:0] (pins 98 to 87). Notes: All buffers use TTL levels. All inputs are driven between 2.4 V and 0.4 V. An internal 50 k pull-up is provided on the 3-STATE, RESET, DS1/CEPT, FRAMER, SYSCLK, CKSEL, MPMODE, MPMUX, CS, MPCLK, JTAGTDI, JTAGTCK, and JTAGTMS pins. An internal 50 k pull-down is provided on the JTAGRST pin.
Power Supply Bypassing
External bypassing is required for each channel. A 1.0 F capacitor must be connected between VDDX and GRNDX. In addition, a 0.1 F capacitor must be connected between VDD and GRND, and a 0.1 F capacitor must be connected between VDDA and GRNDA. Ground plane connections are required for GRNDX, GRND, and GRNDA. Power plane connections are also required for VDDX and VDD. The need to reduce high-frequency coupling into the analog supply (VDDA) may require an inductive bead to be inserted between the power plane and the VDDA pin of each channel. Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness.
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Preliminary Data Sheet October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Outline Diagram
144-Pin TQFP
Dimensions are in millimeters.
22.00 0.20 20.00 0.20 PIN #1 IDENTIFIER ZONE
144 109
1
108
20.00 0.20 22.00 0.20
36
73
37
72
DETAIL A
DETAIL B 1.40 0.05
1.60 MAX SEATING PLANE 0.08 0.50 TYP 1.00 REF 0.05/0.15
0.25 GAGE PLANE SEATING PLANE 0.45/0.75 0.19/0.27
0.106/0.200
0.08 DETAIL B
M
DETAIL A
5-3815(F)r.6
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T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
Preliminary Data Sheet October 2000
Ordering Information
Device Code T - 7630 - - - TL - DB Package 144-Pin TQFP Temperature -40 C to +85 C Comcode (Ordering Number) 107913337
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. N o liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. SLC is a registered trademark of Lucent Technologies.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
October 2000 DS00-191TIC (Replaces DS98-234TIC)

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